Xilinx error xst: 1706 & 1847

How to solve error 1706 & 1847 occur during synthesis of design and
give following messege:
PL$_7>: port <_n2472> of logic node <_n0923> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2468> of logic node
<_n0918> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0917> has no source
ERROR:Xst:1706 - Unit <subbytes_$SPL$_7>: port <_n2466> of logic node
<_n0916> has no source
ERROR:Xst:1847 - Design checking failed
ERROR: XST failed