Xilinx EDK PCI

Jackson Pang · Jul 15, 2004

Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge
core using EDK. I set up the project and configured all the core parameters
correctly. I also double checked the constraint file for pin assignments for
the PCI finger. The compile and programming process goes well without any
error, but I cannot even get my host PC to recognize my development board
with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
Thanks for your input in advance.

joe · Jul 16, 2004

Have you installed a PCI driver for the board on the host PC? What Os are you using?

Jackson Pang · Jul 16, 2004

Joe

Avnet does not make host drivers. Either way it should still show up on the Device Manager in Windows or lspci in Linux as an undefined device if the configuration cycles of the PCI core are working correctly. I tried to find this out with a logic analyzer but no luck. Thanks for you help though.

-Jackson
<joe> wrote in message news:ee878f6.0@webx.sUN8CHnE...
Have you installed a PCI driver for the board on the host PC? What Os are you using?

seb · Jul 19, 2004

Which EDK version do you use ? <br>
Could you paste your MHS file ?

Jackson Pang · Jul 26, 2004

Hi Seb

I used EDK 6.2

Here's the .mhs

PARAMETER VERSION = 2.1.0

PORT clk_40mhz = clk_40mhz, DIR = I, SIGIS = CLK
PORT pci_TRDY_N = pci_TRDY_N, DIR = IO
PORT pci_CBE = pci_CBE, VEC = [0:3], DIR = IO
PORT pci_DEVSEL_N = pci_DEVSEL_N, DIR = IO
PORT pci_FRAME_N = pci_FRAME_N, DIR = IO
PORT pci_AD = pci_AD, VEC = [0:31], DIR = IO
PORT pci_SERR_N = pci_SERR_N, DIR = IO
PORT pci_IDSEL = pci_IDSEL, DIR = I
PORT pci_INTR_A = pci_INTR_A, DIR = O
PORT pci_IRDY_N = pci_IRDY_N, DIR = IO
PORT pci_PAR = pci_PAR, DIR = IO
PORT pci_GNT_N = pci_GNT_N, DIR = I
PORT pci_Freeze = pci_Freeze, DIR = I
PORT pci_PCLK = pci_PCLK, DIR = I
PORT pci_STOP_N = pci_STOP_N, DIR = IO
PORT pci_RST_N = pci_RST_N, DIR = I
PORT pci_REQ_N = pci_REQ_N, DIR = O
PORT pci_PERR_N = pci_PERR_N, DIR = IO
PORT RS232_RX = RS232_RX, DIR = I
PORT RS232_TX = RS232_TX, DIR = O
PORT led_pin = led_pin, VEC = [0:7], DIR = IO
PORT sw_pin = sw_pin, VEC = [0:7], DIR = IO
PORT sys_clk = sys_clk, DIR = I, SIGIS = Clk
PORT sys_rst = sys_rst, DIR = I

BEGIN microblaze
PARAMETER INSTANCE = mblaze
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE DLMB = d_lmb
BUS_INTERFACE ILMB = i_lmb
BUS_INTERFACE DOPB = d_opb
BUS_INTERFACE IOPB = d_opb
PORT CLK = clk_40mhz
PORT INTERRUPT = mblaze_int
END

BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = data
BUS_INTERFACE PORTB = inst
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_bram_cntrl
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = i_lmb
BUS_INTERFACE BRAM_PORT = data
PORT LMB_Clk = clk_40mhz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_bram_cntrl
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = d_lmb
BUS_INTERFACE BRAM_PORT = inst
PORT LMB_Clk = clk_40mhz
END

BEGIN opb_pci
PARAMETER INSTANCE = pci
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00009000
PARAMETER C_HIGHADDR = 0x00009FFF
PARAMETER C_PCIBAR_NUM = 2
PARAMETER C_PCIBAR_LEN_0 = 15
PARAMETER C_PCIBAR2IPIF_0 = 0x00008000
PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 = 1
PARAMETER C_PCI_PREFETCH_0 = 1
PARAMETER C_PCI_SPACETYPE_0 = 1
PARAMETER C_IPIFBAR_NUM = 1
PARAMETER C_IPIF_HIGHADDR_0 = 0x0000FFFF
PARAMETER C_IPIFBAR2PCI_0 = 0x0
PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_0 = 1
PARAMETER C_IPIF_PREFETCH_0 = 1
PARAMETER C_IPIF_SPACETYPE_0 = 1
PARAMETER C_NUM_INTERRUPTS = 13
PARAMETER C_OPB_CLK_PERIOD_PS = 25000
PARAMETER C_CLASS_CODE = 0x028000
PARAMETER C_DEVICE_ID = 0x9050
PARAMETER C_DMA_HIGHADDR = 0x0000A77F
PARAMETER C_DMA_CHAN_TYPE = 0
PARAMETER C_DMA_LENGTH_WIDTH = 15
PARAMETER C_DEV_MIR_ENABLE = 1
PARAMETER C_INCLUDE_DEV_ISC = 1
PARAMETER C_IPIFBAR_1 = 0x0000A600
PARAMETER C_IPIF_HIGHADDR_1 = 0x0000A61F
PARAMETER C_IPIFBAR2PCI_1 = 0x0
PARAMETER C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 = 1
PARAMETER C_IPIF_PREFETCH_1 = 1
PARAMETER C_IPIF_SPACETYPE_1 = 1
PARAMETER C_PCIBAR_1 = 0xFFFFFFF8
PARAMETER C_PCIBAR_LEN_1 = 4
PARAMETER C_PCIBAR2IPIF_1 = 0x0000A600
PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_1 = 1
PARAMETER C_PCI_PREFETCH_1 = 1
PARAMETER C_PCI_SPACETYPE_1 = 1
PARAMETER C_VENDOR_ID = 0x10B7
PARAMETER C_INCLUDE_PCI_CONFIG = 1
PARAMETER C_REV_ID = 0x01
PARAMETER C_MAX_LAT = 0x08
PARAMETER C_MIN_GNT = 0x03
PARAMETER C_NUM_IDSEL = 1
PARAMETER C_DMA_BASEADDR = 0x0000A700
PARAMETER C_PCIBAR_0 = 0xFFFF0008
PARAMETER C_IPIFBAR_0 = 0x00008000
BUS_INTERFACE MSOPB = d_opb
PORT TRDY_N = pci_TRDY_N
PORT OPB_Clk = clk_40mhz
PORT CBE = pci_CBE
PORT DEVSEL_N = pci_DEVSEL_N
PORT FRAME_N = pci_FRAME_N
PORT AD = pci_AD
PORT SERR_N = pci_SERR_N
PORT IDSEL = pci_IDSEL
PORT INTR_A = pci_INTR_A
PORT IRDY_N = pci_IRDY_N
PORT PAR = pci_PAR
PORT GNT_N = pci_GNT_N
PORT Freeze = pci_Freeze
PORT PCLK = pci_PCLK
PORT STOP_N = pci_STOP_N
PORT RST_N = pci_RST_N
PORT REQ_N = pci_REQ_N
PORT PERR_N = pci_PERR_N
END

BEGIN opb_uartlite
PARAMETER INSTANCE = uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x0000A000
PARAMETER C_HIGHADDR = 0x0000A0FF
PARAMETER C_DATA_BITS = 8
PARAMETER C_CLK_FREQ = 40000000
PARAMETER C_BAUDRATE = 9600
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
BUS_INTERFACE SOPB = d_opb
PORT OPB_Clk = clk_40mhz
PORT RX = RS232_RX
PORT TX = RS232_TX
PORT Interrupt = net_gnd
END

BEGIN opb_jtag_uart
PARAMETER INSTANCE = jtag_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x0000A100
PARAMETER C_HIGHADDR = 0x0000A1FF
BUS_INTERFACE SOPB = d_opb
PORT Interrupt = net_gnd
PORT OPB_Clk = clk_40mhz
END

BEGIN lmb_v10
PARAMETER INSTANCE = d_lmb
PARAMETER HW_VER = 1.00.a
PORT SYS_Rst = sys_rst
PORT LMB_Clk = clk_40mhz
END

BEGIN lmb_v10
PARAMETER INSTANCE = i_lmb
PARAMETER HW_VER = 1.00.a
PORT SYS_Rst = sys_rst
PORT LMB_Clk = clk_40mhz
END

BEGIN opb_v20
PARAMETER INSTANCE = d_opb
PARAMETER HW_VER = 1.10.b
PARAMETER C_BASEADDR = 0xFF020000
PARAMETER C_HIGHADDR = 0xFF0201FF
PARAMETER C_PROC_INTRFCE = 1
PORT SYS_Rst = sys_rst
PORT OPB_Clk = clk_40mhz
END

BEGIN opb_gpio
PARAMETER INSTANCE = led
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x0000A200
PARAMETER C_HIGHADDR = 0x0000A2FF
PARAMETER C_GPIO_WIDTH = 8
BUS_INTERFACE SOPB = d_opb
PORT OPB_Clk = clk_40mhz
PORT GPIO_IO = led_pin
END

BEGIN opb_gpio
PARAMETER INSTANCE = sw
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x0000A300
PARAMETER C_HIGHADDR = 0x0000A3FF
PARAMETER C_GPIO_WIDTH = 8
BUS_INTERFACE SOPB = d_opb
PORT GPIO_IO = sw_pin
PORT OPB_Clk = clk_40mhz
END

BEGIN opb_intc
PARAMETER INSTANCE = intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x0000A400
PARAMETER C_HIGHADDR = 0x0000A4FF
PARAMETER C_IRQ_IS_LEVEL = 0
BUS_INTERFACE SOPB = d_opb
PORT OPB_Clk = clk_40mhz
PORT Intr = bar_int_Intr
PORT Irq = mblaze_int
END

BEGIN opb_interrupt_generator
PARAMETER INSTANCE = bar_int
PARAMETER C_BASEADDR = 0x0000A600
PARAMETER C_HIGHADDR = 0x0000A60F
BUS_INTERFACE SOPB = d_opb
PORT opb_clk = sys_clk
PORT Interrupt = bar_int_Intr
END

BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = pk_mem
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x00008000
PARAMETER C_HIGHADDR = 0x0000FFFF
END

"seb" <sebastien.longueville@fr.thalesgroup.com> wrote in message news:ee878f6.2@webx.sUN8CHnE...
Which EDK version do you use ?
Could you paste your MHS file ?

seb · Jul 27, 2004

It looks good. <br>
Try to get a PCI design example from Avnet to underline differences

Erik Widding · Jul 28, 2004

"Jackson Pang" <jacpang@cisco.com> wrote in message news:<1089908158.304115@sj-nntpcache-3>...

Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge
core using EDK. I set up the project and configured all the core parameters
correctly. I also double checked the constraint file for pin assignments for
the PCI finger. The compile and programming process goes well without any
error, but I cannot even get my host PC to recognize my development board
with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the
opb pci. It was our experience with this version of the core that
the PCI target read transactions will hang the PCI bus. This bug
was reported Nov 2003. I did a very cursory search of the answers
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your
current problem. I would recomend that you use a more recent
revision of the core than v1_00_b. I would assume that this bug is
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Jackson Pang · Jul 28, 2004

Hi Seb

Avnet doesn't use EDK as far as I know and they only gave us the bitmap of a PCIX implementation to show that the card works. I will ask them again about whether they have done EDK implementation since we bought the board.

Thanks again.
Jackson
<seb> wrote in message news:ee878f6.4@webx.sUN8CHnE...
It looks good.
Try to get a PCI design example from Avnet to underline differences

Jackson Pang · Jul 28, 2004

Hi Erik

Thanks so much for your input and offer. I am working for a research group
at Cal Poly and we have very limited funds. It is a learning experience for
us to be able use PCI with our intelligent NIC. However, due to our license
agreement with Xilinx, we cannot get any technical support to help us pin
point what is wrong with our PCI/OPB core implementation. I'd also like to
try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a better
understanding of the core. I'd like to know if you're willing to share your
OPB/PCI interface wrapper implementation experience.

Thanks for your help
Jackson

FYI - our project is on the web at http://netprl.calpoly.edu

"Erik Widding" <widding@birger.com> wrote in message
news:afe40eec.0407271638.28365ac6@posting.google.com...

"Jackson Pang" <jacpang@cisco.com> wrote in message
news:<1089908158.304115@sj-nntpcache-3>...
Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI
bridge
core using EDK. I set up the project and configured all the core
parameters
correctly. I also double checked the constraint file for pin assignments
for
the PCI finger. The compile and programming process goes well without
any
error, but I cannot even get my host PC to recognize my development
board
with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the
opb pci. It was our experience with this version of the core that
the PCI target read transactions will hang the PCI bus. This bug
was reported Nov 2003. I did a very cursory search of the answers
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your
current problem. I would recomend that you use a more recent
revision of the core than v1_00_b. I would assume that this bug is
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Austin Lesea · Jul 28, 2004

Jackson,

Support for the Universities is provided by:

http://www.xilinx.com/univ/

And not through the regular Xilinx hotline system.

http://xup.msu.edu/

Michigan State University is tasked with being the "University Hotline"
for our hundreds of thousands of students world wide. This allows the
commercial hotline to provide the best possible solutions to our 'paying
customers', and also allows students to work directly with their peers
who have been trained by Xilinx to answer their questions.

I hope no one is confused enough (by your email domain)to think that
Xilinx has a license that prevents the support of a product!

Austin

Jackson Pang wrote:

Hi Erik

Thanks so much for your input and offer. I am working for a research group
at Cal Poly and we have very limited funds. It is a learning experience for
us to be able use PCI with our intelligent NIC. However, due to our license
agreement with Xilinx, we cannot get any technical support to help us pin
point what is wrong with our PCI/OPB core implementation. I'd also like to
try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a better
understanding of the core. I'd like to know if you're willing to share your
OPB/PCI interface wrapper implementation experience.

Thanks for your help
Jackson

FYI - our project is on the web at http://netprl.calpoly.edu

"Erik Widding" <widding@birger.com> wrote in message
news:afe40eec.0407271638.28365ac6@posting.google.com...

"Jackson Pang" <jacpang@cisco.com> wrote in message

news:<1089908158.304115@sj-nntpcache-3>...

Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI

bridge

core using EDK. I set up the project and configured all the core

parameters

correctly. I also double checked the constraint file for pin assignments

for

the PCI finger. The compile and programming process goes well without

any

error, but I cannot even get my host PC to recognize my development

board

with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the
opb pci. It was our experience with this version of the core that
the PCI target read transactions will hang the PCI bus. This bug
was reported Nov 2003. I did a very cursory search of the answers
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your
current problem. I would recomend that you use a more recent
revision of the core than v1_00_b. I would assume that this bug is
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Jackson Pang · Jul 28, 2004

sorry for the possible confusion. my messages on this forum does not reflect
my current employer's opinion. However, I do admit that the quality of
support on XUP is very poor. But then again, we get what we pay for.

thanks for clearing things up Austin

Jackson Pang

"Austin Lesea" <austin@xilinx.com> wrote in message
news:4107D527.7050801@xilinx.com...

Jackson,

Support for the Universities is provided by:

http://www.xilinx.com/univ/

And not through the regular Xilinx hotline system.

http://xup.msu.edu/

Michigan State University is tasked with being the "University Hotline"
for our hundreds of thousands of students world wide. This allows the
commercial hotline to provide the best possible solutions to our 'paying
customers', and also allows students to work directly with their peers
who have been trained by Xilinx to answer their questions.

I hope no one is confused enough (by your email domain)to think that
Xilinx has a license that prevents the support of a product!

Austin

Jackson Pang wrote:

Hi Erik

Thanks so much for your input and offer. I am working for a research
group
at Cal Poly and we have very limited funds. It is a learning experience
for
us to be able use PCI with our intelligent NIC. However, due to our
license
agreement with Xilinx, we cannot get any technical support to help us
pin
point what is wrong with our PCI/OPB core implementation. I'd also like
to
try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a
better
understanding of the core. I'd like to know if you're willing to share
your
OPB/PCI interface wrapper implementation experience.

Thanks for your help
Jackson

FYI - our project is on the web at http://netprl.calpoly.edu

"Erik Widding" <widding@birger.com> wrote in message
news:afe40eec.0407271638.28365ac6@posting.google.com...

"Jackson Pang" <jacpang@cisco.com> wrote in message

news:<1089908158.304115@sj-nntpcache-3>...

Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI

bridge

core using EDK. I set up the project and configured all the core

parameters

correctly. I also double checked the constraint file for pin
assignments

for

the PCI finger. The compile and programming process goes well without

any

error, but I cannot even get my host PC to recognize my development

board

with the PCI bitmap. I am using Avnet's Virtex II PCI Development
Board.
Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the
opb pci. It was our experience with this version of the core that
the PCI target read transactions will hang the PCI bus. This bug
was reported Nov 2003. I did a very cursory search of the answers
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your
current problem. I would recomend that you use a more recent
revision of the core than v1_00_b. I would assume that this bug is
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Austin Lesea · Jul 28, 2004

Jackson,

Poor support on XUP from MSU? Really? I would like to know of your
experience. Perhaps your work is too advanced for their knowledge base?

You may email me directly at austin ___ @ ___ xilinx ___ . ____ com
(remove puncuation).

I am sure there are other universities that would like to provide what
MSU does (for the benefits they gain from us), so letting us know how
well our partners perform is beneficial.

If you are working with EDK, and the PPC, and the various busses, you
may be doing work that is well advanced ahead of what the XUP is able to
provide right now. This is useful for us to know.

By donating millions of dollars to education, we do not serve ourselves
by then ignoring the support (so we do not).

We also can not allow the XUP patrons to use the commercial support as
that would adversely impact business.

A delicate balance.

Austin

Jackson Pang wrote:

sorry for the possible confusion. my messages on this forum does not reflect
my current employer's opinion. However, I do admit that the quality of
support on XUP is very poor. But then again, we get what we pay for.

thanks for clearing things up Austin

Jackson Pang

"Austin Lesea" <austin@xilinx.com> wrote in message
news:4107D527.7050801@xilinx.com...

Jackson,

Support for the Universities is provided by:

http://www.xilinx.com/univ/

And not through the regular Xilinx hotline system.

http://xup.msu.edu/

Michigan State University is tasked with being the "University Hotline"
for our hundreds of thousands of students world wide. This allows the
commercial hotline to provide the best possible solutions to our 'paying
customers', and also allows students to work directly with their peers
who have been trained by Xilinx to answer their questions.

I hope no one is confused enough (by your email domain)to think that
Xilinx has a license that prevents the support of a product!

Austin

Jackson Pang wrote:

Hi Erik

Thanks so much for your input and offer. I am working for a research

group

at Cal Poly and we have very limited funds. It is a learning experience

for

us to be able use PCI with our intelligent NIC. However, due to our

license

agreement with Xilinx, we cannot get any technical support to help us

pin

point what is wrong with our PCI/OPB core implementation. I'd also like

to

try implementing the OPB/PCI wrapper to the Xilinx Logicore to get a

better

understanding of the core. I'd like to know if you're willing to share

your

OPB/PCI interface wrapper implementation experience.

Thanks for your help
Jackson

FYI - our project is on the web at http://netprl.calpoly.edu

"Erik Widding" <widding@birger.com> wrote in message
news:afe40eec.0407271638.28365ac6@posting.google.com...

"Jackson Pang" <jacpang@cisco.com> wrote in message

news:<1089908158.304115@sj-nntpcache-3>...

Hello

I'd like to know if anybody had any success in using Xilinx OPB/PCI

bridge

core using EDK. I set up the project and configured all the core

parameters

correctly. I also double checked the constraint file for pin

assignments

for

the PCI finger. The compile and programming process goes well without

any

error, but I cannot even get my host PC to recognize my development

board

with the PCI bitmap. I am using Avnet's Virtex II PCI Development

Board.

Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the

opb pci. It was our experience with this version of the core that
the PCI target read transactions will hang the PCI bus. This bug
was reported Nov 2003. I did a very cursory search of the answers
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your
current problem. I would recomend that you use a more recent
revision of the core than v1_00_b. I would assume that this bug is
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Erik Widding · Jul 28, 2004

widding@birger.com (Erik Widding) wrote in message news:<afe40eec.0407271638.28365ac6@posting.google.com>...

As we could not wait for the bugs to be fixed, we developed a PCI
to PLB, and PCI to OPB bridge, with DMA (pci master) support on
the PLB side. This core supports bursting on all but the OPB buses
at present. We can make this available on a commercial basis. It
is wrapped around the Xilinx PCI logicore, which I should note is
one of the best documented, most flexible, pieces of IP we have
ever used.

It has been brought to my attention that the above paragraph appears
to be an offer to redistribute the Xilinx PCI Logicore. It was my
intention to offer our wrapper sans the Xilinx core. I appologize
for any confusion this has caused.

Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

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