Xilinx DCM LOCKED signal valid after input clock returns?

[Barry Brown]

OK, the DCM input clock goes away, and I understand the LOCKED signal is not
valid. After the input clock comes back, can you rely on the LOCKED signal
to indicate that a DCM reset pulse is needed?

And ditto that question for the STATUS(2) signal when you are using the
CLKFX output?

I'm trying to avoid creating an extra independent clock (with some little
oscillator) that would be used to clock a state machine to generate the DCM
reset pulse when STATUS(1) indicates loss of input clock. So I thought to
use the input clock itself for the state machine, and test the LOCKED signal
to decide about reset. After all, there's no point in resetting the DCM
until after its input clock has returned.

I hoped the Xilinx website might have an example circuit to handle DCM
reset, but I couldn't find anything.

Barry Brown

 

[Austin Lesea]

Barry,

Within a few thousands of clocks after the clock has returned (depending on the
settings of the jitter filters), the DLL will either be locked, or LOCK will go
low (indicating that the DLL has run off the ends of the delay lines due to the
interruption), or CLKIN_STOPPED will still be high indicating the clock really
did not come back as expected.

If the CLKFX output is also being used, and interruption at all will lead to the
CLKFX_STOPPED bit asserting high.

Easier to just use LOCKED going low after it has already gone high, OR
CLKIN_STOPPED going high OR CLKFX_STOPPED going high as your trigger to reset.

Hope this helps in your little state machine design.

Austin

Barry Brown wrote:

OK, the DCM input clock goes away, and I understand the LOCKED signal is not
valid. After the input clock comes back, can you rely on the LOCKED signal
to indicate that a DCM reset pulse is needed?

And ditto that question for the STATUS(2) signal when you are using the
CLKFX output?

I'm trying to avoid creating an extra independent clock (with some little
oscillator) that would be used to clock a state machine to generate the DCM
reset pulse when STATUS(1) indicates loss of input clock. So I thought to
use the input clock itself for the state machine, and test the LOCKED signal
to decide about reset. After all, there's no point in resetting the DCM
until after its input clock has returned.

I hoped the Xilinx website might have an example circuit to handle DCM
reset, but I couldn't find anything.

Barry Brown