Xilinx Chipscope Sample rate

T

Tobias Möglich

Guest
Hello,

I use Xilinx Chipscope for ISE 6.1.
My question. What's the sample rate. I couldn't find any documentation
about it.

If I use a fast clock signal in my design, I do have to use a big sample
rate, isn't it ?
Otherwise I won' get the exact result. Right?


Greatings, Tobias Möglich
 
The sample rate depends on the speed grade of the part, especially the block RAM timing, and how full the part already is without ChipScope. Fairly full designs cause larger routing delays. You'll have to build your design with ChipScope to see if it meets your timing specs.
 
Tobias Möglich wrote:

Hello,

I use Xilinx Chipscope for ISE 6.1.
My question. What's the sample rate. I couldn't find any documentation
about it.
The ILA-core has a clock input. The data is then sampled on the rising
Click to expand...
or falling edge (depending on how you set it up) of that clock. Usually
you just pick the fastest clock signal in your design for that.

If I use a fast clock signal in my design, I do have to use a big sample
rate, isn't it ?
Otherwise I won' get the exact result. Right?
Basically yes. In ChipScope this is - at least most of the time -
Click to expand...
nothing you have to worry about, since the clocks to update the signals
and to sample them are the same. The only thing you should take care of
is that the sample clock is synchronous to the signals you want to analyze.

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])
 
Thank you for your advice.
But in the CoreGenerator I could only choose wether to use the rising or the
falling edge.
I could not find which clock is meant.
I use a development board from Xilinx ( --> Spartan-IIE-LC).
I know that a 100 MHz oscillator is used in the design. It is connected to one
of the 4 global clock nets.
I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue
or a dialog box in the GUI to choose
which clock signal of the design is used for sampling the signals.

Can you tell me where to choose it?

Tobias


>
 
Tobias Möglich wrote:
Thank you for your advice.
But in the CoreGenerator I could only choose wether to use the rising or the
falling edge.
I could not find which clock is meant.
I use a development board from Xilinx ( --> Spartan-IIE-LC).
I know that a 100 MHz oscillator is used in the design. It is connected to one
of the 4 global clock nets.
I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue
or a dialog box in the GUI to choose
which clock signal of the design is used for sampling the signals.

Can you tell me where to choose it?
You assign the clock when you instantiate the ILA in your design.
Click to expand...
CoreGenerator can generate example VHDL-files for you, if you check the
corresponding option. Then you can assign whatever clock you like to the
"CLK"-port of the ILA core in the instantiation.

With Chipscope Pro comes a "Core Inserter" you can use. It offers a GUI
to make all the signal connections, including the clock. That way, you
don't have to instantiate ILA/ICON in your design.

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])
 
Sean Durkin wrote:

Tobias Möglich wrote:
Thank you for your advice.
But in the CoreGenerator I could only choose wether to use the rising or the
falling edge.
I could not find which clock is meant.
I use a development board from Xilinx ( --> Spartan-IIE-LC).
I know that a 100 MHz oscillator is used in the design. It is connected to one
of the 4 global clock nets.
I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue
or a dialog box in the GUI to choose
which clock signal of the design is used for sampling the signals.

Can you tell me where to choose it?
You assign the clock when you instantiate the ILA in your design.
CoreGenerator can generate example VHDL-files for you, if you check the
corresponding option. Then you can assign whatever clock you like to the
"CLK"-port of the ILA core in the instantiation.

With Chipscope Pro comes a "Core Inserter" you can use. It offers a GUI
to make all the signal connections, including the clock. That way, you
don't have to instantiate ILA/ICON in your design.
Click to expand...
Ouuh yes - I see. I use the "Core Inserter". And I already connected the clock
signal to a certain oscillator in my hardware.
I forgot that I did it. And now I wondered why it worked.
Thank you very much.

Question: Is it possible to see the clock signal also in the scope?
Or ist only possible to see the Data/ and trigger signals?

Tobias
 
Tobias Möglich wrote:
Question: Is it possible to see the clock signal also in the scope?
Or ist only possible to see the Data/ and trigger signals?
Well, you can add clock signals to the data signals you want to sample
Click to expand...
like any other signal... But since you always sample at the rising or
falling edge of your clock, it will always be 1 or 0, respectively, so
that's not really useful.

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])
 
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