Xilinx Block RAM Init

[Arlen]

I have a Xilinx Spartan IIE device and it has built in block rams that I would like to use for effectively a ROM design. <p>All the documentation that I can find that Xilinx provides seems to be rather old (2000-2001) and thus doesn't work on the current tools (Webpack 6.2). Does anyone know how to specifiy block ram initialization values in verilog using Webpack 6.2? <p>Thanks, <BR>
Arlen

 

[Eric Crabill]

Hi,

Go to http://www.engr.sjsu.edu/crabill and download lab
assignment #5, including the zip of the project files.
The main point of this lab is to learn how to use BlockRAM
primitives to build a large ROM in a Spartan-IIE device.
It's done in Verilog.

Eric

Arlen wrote:

I have a Xilinx Spartan IIE device and it has built in block
rams that I would like to use for effectively a ROM design.

 

[John Retta]

You should take a look at your Xilinx Library Guide installed
in the doc directory tree.Name of the file is lib.pdf. The RAMB4
section describes the various Block RAM configurations, as well
as examples on initialization.
Reason that I mention this document, is it is excellant reference for
learning all primitives within various Xilinx FPGA families.

Here is some sample code
(Note, the INIT constants end at INIT_0F for a 4K block RAM) :

defparam pin_lookup_512x8.INIT_00 =
256'h3817391841204215321133123514360926052706290830034745440123022448;
defparam pin_lookup_512x8.INIT_01 =
256'h0000000000000000000000000000000000000000000000506261575654535121;
defparam pin_lookup_512x8.INIT_02 =
256'h4120421732333435363738310325262728293024454443220123024650494847;
defparam pin_lookup_512x8.INIT_03 =
256'h0000000000000000000000000000000000000051585756555453522139184019;

RAMB4_S8 pin_lookup_512x8 (
..CLK (cr_clk_100mhz),
..RST (cr_100m_rst),
..WE (1'b0),
..EN (1'b1),
..ADDR ({1'b0, err_raw_val}),
..DI (8'h00),
..DO (bcd_pin_convert)
);

--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc. (Colorado Based Xilinx Consultant)

email : jretta@rtc-inc.com
web : www.rtc-inc.com


"Arlen" &lt;a_cox@pacific.edu&gt; wrote in message
news:ee83f7d.-1@WebX.sUN8CHnE...
I have a Xilinx Spartan IIE device and it has built in block rams that I
would like to use for effectively a ROM design.
All the documentation that I can find that Xilinx provides seems to be
rather old (2000-2001) and thus doesn't work on the current tools (Webpack
6.2). Does anyone know how to specifiy block ram initialization values in
verilog using Webpack 6.2?
Thanks,
Arlen