xilinx 70% tracking rule

[guille]

Hi there,

Sorry for another Xilinx-specific question

Peter Alfke mentioned this 70% tracking rule for timing parameters,
which basically says that if a parameter is at its max value, then all
other parameters are between 70% and 100% of their guaranteed maximums.
For Xilinx CPLDs, at least.

This makes a lot of sense from a physical standpoint, and I've seen
it mentioned in other posts too.

I have only one question, if somebody can help. How is this 70% figure
calculated, or estimated? Is it based on lab results only, or was it
first derived analytically in some way or another and then verified
experimentally? (I believe the latter). I'm curious about the physics
involved.

Thanks,
Guillermo Rodriguez

 

[jim granville]

guille wrote:

Hi there,

Sorry for another Xilinx-specific question

Peter Alfke mentioned this 70% tracking rule for timing parameters,
which basically says that if a parameter is at its max value, then all
other parameters are between 70% and 100% of their guaranteed maximums.
For Xilinx CPLDs, at least.

This makes a lot of sense from a physical standpoint, and I've seen
it mentioned in other posts too.

I have only one question, if somebody can help. How is this 70% figure
calculated, or estimated? Is it based on lab results only, or was it
first derived analytically in some way or another and then verified
experimentally? (I believe the latter). I'm curious about the physics
involved.

It will be experimental / empirical.
It derives from all gates being on the same wafer (thus largely process
track), and at the same Vcc, and similar Temperatures.
Normal process tracking these days is very good, and a portion of
variance will be physical location dependant, but it's easier to
umbrella that under process or min/max timing.

-jg

 

[Paul Leventis (at home)]

I don't know whether 70% is the correct number or not, as it depends on many
things and on how sophisticated the timing model was for the "maximum"
numbers in the first place. But here are a few other phenomena to add to
the laundry list:
- Differences between rising and falling delay (is the max # worst case of
two?)
- Localized IR drop in power network causes differences in Vdd seen by
transistors in different areas of chip
- Temperature gradients due to differing power densities
- Unmodeled differences in physical structure between similar resources.
For example, in a crude timing model all wires of length 4 could be given
same delay, but in reality there are differences in what metal they are
adjacent to, they could have slightly different lengths, etc. Or trace
lengths for two IOs could be slightly different. Of course, whether this
need be included in the 70% depends on whether timing model accounts for
this stuff or not.
- Cross-coupling, which can speed up (or slow down) a signal.

Also, some aspects of process track very well across a die (e.g. metal,
dielectric thickness), while others do not -- for example, tranistor
threshold voltage can vary significantly from one transistor to the next due
to the stoicastic nature of implants/dopants, though the average Vt value
will be similar across the die. Since timing paths include multiple
transistors, you tend to get an averaging effect, but still, it is another
thing to worry about.

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I hope
-- imagine having to worry about all this stuff when doing your ASIC?

Regards,

Paul Leventis
Altera Corp.

It will be experimental / empirical.
It derives from all gates being on the same wafer (thus largely process
track), and at the same Vcc, and similar Temperatures.
Normal process tracking these days is very good, and a portion of
variance will be physical location dependant, but it's easier to
umbrella that under process or min/max timing.

 

[guille]

"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<7gKPb.46671$lGr.8430@twister01.bloor.is.net.cable.rogers.com>...

I don't know whether 70% is the correct number or not, as it depends on many
things and on how sophisticated the timing model was for the "maximum"
numbers in the first place. But here are a few other phenomena to add to
the laundry list:
[...]

Interesting! Thanks for your input.

This 70% figure was for Xilinx CPLDs. What would be a good estimation
for Altera devices?

Does Altera document tracking properties for their devices? (either
'officially' in datasheets, or in application notes). Just curious.

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I hope
-- imagine having to worry about all this stuff when doing your ASIC?

I can imagine

Guillermo Rodriguez

 

[Rudolf Usselmann]

"Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote in message news:<7gKPb.46671$lGr.8430@twister01.bloor.is.net.cable.rogers.com>...
....

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I hope
-- imagine having to worry about all this stuff when doing your ASIC?

Yes, imagine working with a part that comes with a data
sheet with 100% clearly defined timing for each cell !
Just open the data sheet and get 100% clear information.

(Routing delays are undefined until Synthesis and P&R for both.)

Regards,

Paul Leventis
Altera Corp.

This BS marketing from FPGA companies is 80% nonsenseand
5% Truth. The remaining 15% are pure lies.

Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
...............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools

 

[Peter Alfke]

Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.
I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.
For some reason the world is rapidly converting to FPGA. Last year there
were less than 1500 new ASIC designs and probably 100 000 new designs
using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
they come with a hefty price tag, long manufacturing time, risk and
inflexibility. That's why most of us prefer FPGAs. It is also reflected
in the name of this ng.

So, Rudi, if you want to post here, say something meaningful, and do not
just blurt out unsubstantiated insults. Hurts your reputation more than mine...

Peter Alfke,
============================================
Rudolf Usselmann wrote:

This BS marketing from FPGA companies is 80% nonsenseand
5% Truth. The remaining 15% are pure lies.

Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools

 

[Ralph Malph]

Peter Alfke wrote:

Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.
I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.

I am not looking to get into this argument, but certainly there are lies
that marketing tells. I caught Linear Tech in an outright lie in an ad
that claimed a switcher could be built in a certain amount of board
space. I called and asked for info on that design and was told that
there *was no design*. It was a number that no one could even explain
how they came up with.

Closer to home is the ever present lie in the Xilinx data sheets about
logic cell count. The last time I checked, counting involved actually
counting things. Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.

This may be a small case, but so much of what semi companies put out in
ads and in literature is clearly hyped. You may not like it as an
engineer, but it is the truth.

 

[Peter Alfke]

Ralph, you don't find me quoting those "12% inflated" numbers.
I hate thatfake arithmetic, but I have at times explained the reasoning
behind it, without endorsing it. It seems to be a trap without an easy
exit. Hell, we don't need those lousy 12.5% to look good. This is stuff
from a bygone era.
Anyhow, this does not make it "80% nonsense and 15% lies".
I have a right to defend myself and my company against silly
accusations. We don't have to agree always, but we need not accept insults.

Peter Alfke
=========================================
Ralph Malph wrote:

Closer to home is the ever present lie in the Xilinx data sheets about
logic cell count. The last time I checked, counting involved actually
counting things. Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.

This may be a small case, but so much of what semi companies put out in
ads and in literature is clearly hyped. You may not like it as an
engineer, but it is the truth.

 

[Kolja Sulimma]

Wow, a real flame war at comp.arch.fpga.

Rudi: I guess from your asic design experience you can guess, why the
timing for routing is not well defined before the routing is done.

But mostly I am posting as a response to Peter:
Success of a product does not actually contradict overly optimistic
marketing claims. At least short time success should be able to be
improved by marketing lies, don't you think?

You should not be offended personally. You now that the information
from you and austin is always better and more detailed and often very
different from what's in datsheets let alone the press releases.
So if a lot of people dislike the press releases, this does not mean,
they do not respect you. And many of them use Xilinx, so they do not
think to bad of the product either.

But there is reason not to like Xilinx marketing.

Remember the press release that claimed prices that are valid NOW but
not before Q4/2004? I do not use "now" that way.
Or Insight who send me spam that told me I could get XC3S200 in volume
now but at the phone told me I could not even get samples?

The problem for us engineers is, that our customers read the press
releases.
And we always look like idiots when we have to explain them, that we
can not do that what Xilinx suggests. Or not yet. Or only at 20x the
price. Or only if they buy a million parts.

Regards,

Kolja


Peter Alfke <peter@xilinx.com> wrote in message news:<401011AA.9D090355@xilinx.com>...

Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.
I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.
For some reason the world is rapidly converting to FPGA. Last year there
were less than 1500 new ASIC designs and probably 100 000 new designs
using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
they come with a hefty price tag, long manufacturing time, risk and
inflexibility. That's why most of us prefer FPGAs. It is also reflected
in the name of this ng.

So, Rudi, if you want to post here, say something meaningful, and do not
just blurt out unsubstantiated insults. Hurts your reputation more than mine...

Peter Alfke,
============================================
Rudolf Usselmann wrote:

This BS marketing from FPGA companies is 80% nonsenseand
5% Truth. The remaining 15% are pure lies.

Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
..............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools

 

[Mike Treseler]

Ralph Malph wrote:

logic cell count. The last time I checked, counting involved actually
counting things. Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.

Why would an engineer be concerned
about such estimates when he can run a
synthesis on his design and
get the *exact utilization* ?

-- Mike Treseler

 

[Ralph Malph]

Mike Treseler wrote:

Ralph Malph wrote:

logic cell count. The last time I checked, counting involved actually
counting things. Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.

Why would an engineer be concerned
about such estimates when he can run a
synthesis on his design and
get the *exact utilization* ?

-- Mike Treseler

Because some engineers have to consider costs and need to know how large
a part is before it is designed into a board. Not all FPGAs are used
like ASICs. Often they are used like FPGAs where designs are added to
the board well after it is in the field. So the only analysis that can
be done at the time of part selection is paper design based on the
*published* information. If no one ever needed the info in the data
sheets, why would they publish them?

 

[Rudolf Usselmann]

Peter Alfke <peter@xilinx.com> wrote in message news:<401011AA.9D090355@xilinx.com>...

Strong words, Rudi !
But unless you can substantiate your claims, we will ignore them as your
kind of BS.

Which part in my post was unclear ???

Let me break it down for you:

Paul Leventis wrote:

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I hope
-- imagine having to worry about all this stuff when doing your ASIC?

Only seldome have I been able to repeat a synthesis run with
FPGAs and get exactly the same results every time (if I don't
make changes). Running FPGA synthesis is like throwing the dies
in Las Vegas. Funny enough, I can run Synopsys Design Compiler
100 times in a raw and always get the same result.

Besides what is he trying to say ? ASIC vendors don't do
timing models and don't do characterization ? Hmm, anybody
from TSMC, or UMC, or any other ASIC vendor who would like
to comment ?

FPGA guys always look at a FPGA and tell everybody how
cheap they are. They never include the cost for a PROM,
and if they do they always use the cheapest ROM, and then
tell you how you can easily change the configuration.
However they never tell you in advance that the ISP ROM
cost just as much as a (small) FPGA. Hmm, that deception
in my eyes.

I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.

I didn't anywhere in my post refer to you or mantion your name.

I was replying to the writings of Paul Leventis. It is not my
intent to search the archives and evaluate what you have
written or not, and judge you. I know you and Paul, and many
other from both companies provide excellent tech support.
So why, oh why, do some guys throw in the occasional marketing
crap ???

For some reason the world is rapidly converting to FPGA. Last year there
were less than 1500 new ASIC designs and probably 100 000 new designs
using FPGAs. Many of us in this ng are aware of the ASIC advantages, but
they come with a hefty price tag, long manufacturing time, risk and
inflexibility. That's why most of us prefer FPGAs. It is also reflected
in the name of this ng.

Last couple of years where plagued by bad economy. We saw
very few ASIC designs. A large factor why FPGA sales have
been growing is because they are getting big and fast enough
to be used in ASIC modeling and prototyping. I can't envision
a $1000 US FPGA going in to many designs. That are very
special situations - not the norm. In my opinion, FPGA are not
taking market share away from ASICS. Thats where Structured
ASICS and Gate Arrays come in.

The reason IMHO, is that, FPGAS are getting big and fast and
open up new areas and possibilities that where before
impossible to achieve.

So, Rudi, if you want to post here, say something meaningful,and do not
just blurt out unsubstantiated insults. Hurts your reputation more than mine...

Peter Alfke,

Well, I hope this was meaningfully and substantial. And
don't worry, marketing crap will not hurt my reputation,
but yours ... you are telling lies not me ...

rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
...............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools

 

[Ray Andraka]

Try floorplanning. If you floorplan an FPGA, you get repeatable results.

Rudolf Usselmann wrote:

Only seldome have I been able to repeat a synthesis run with
FPGAs and get exactly the same results every time (if I don't
make changes). Running FPGA synthesis is like throwing the dies
in Las Vegas. Funny enough, I can run Synopsys Design Compiler
100 times in a raw and always get the same result.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Paul Leventis (at home)]

Hi Rudolf,

Let's examine my conclusion again:

But this is why FPGA companies have timing modeling and characterization
groups, and part of why FPGAs are slowly taking over the world (or so I
hope
-- imagine having to worry about all this stuff when doing your
ASIC?

The last bit was a somewhat vague dig at ASICs -- to some degree, I'm
smokin' a bit of the FPGA marketing dope. But I still believe there is
truth to this statement. I am not claiming that ASICs lack timing models,
nor that there aren't tools to analyse the myriad of phenomena that one must
worry about when eeking the most performance out of them. I do suppose a
user has the choice of sticking with a conservative view of timing, leaving
some performance on the table for guard-band (while still exceeding the
performance of an FPGA), and making their life easier in this department.
However, I think you would be hard-pressed to argue that it is as easy or
easier to design to an ASIC as it is to design to an FPGA...

Only seldome have I been able to repeat a synthesis run with
FPGAs and get exactly the same results every time (if I don't
make changes). Running FPGA synthesis is like throwing the dies
in Las Vegas. Funny enough, I can run Synopsys Design Compiler
100 times in a raw and always get the same result.

I'm not sure how synthesis repeatibility is related to my discussion of
timing-related phenomena. Regardless, you should get the same answer out of
our CAD tools every time you run them with the same input on the same
machine. If you don't, this is a bug and should be reported to Altera -- I
know Vaughn's team just loves hunting down non-determinism issues. Sucks to
be the engineer who draws the short-straw on those bugs...

Besides what is he trying to say ? ASIC vendors don't do
timing models and don't do characterization ? Hmm, anybody
from TSMC, or UMC, or any other ASIC vendor who would like
to comment ?

He was not trying to say that. Altera and other FPGA vendors would be
screwed if that were the case. Who do you think we're relying on the for
the underlying models we use for telling you your timing?

FPGA guys always look at a FPGA and tell everybody how
cheap they are. They never include the cost for a PROM,
and if they do they always use the cheapest ROM, and then
tell you how you can easily change the configuration.
However they never tell you in advance that the ISP ROM
cost just as much as a (small) FPGA. Hmm, that deception
in my eyes.

In the design of Cyclone (our low-cost family), we kept in mind overall
system cost, including the required PROM. This is why we added the
active-serial programming mode, a matching family of low-cost serial
programming devices, and the bitstream compression feature. If you look at
our web page on our active serial devices
(http://www.altera.com/products/devices/serialcfg/features/scg-adv_features.
html) you will see a marketing chart, complete with vague x-axis, examining
total cost of device + programming solution. A thorough treatise of the
subject it is not, but we're not trying to deceive anyone.

I am an engineer, and I do not make marketing claims, and neither do I
publish 80% nonsense and 15% lies.

I didn't anywhere in my post refer to you or mantion your name.

Ah, come now -- Peter's had a few posts with less than 100% truth at times
too ;-)

My original posting contained 1425 characters, of which 114 were detected to
the marketing crap in the last paragraph. So while not quite 80% non-sense
and 15% lies, that's about 8% questionable/non-technical content, more than
I typically strive for.

So why, oh why, do some guys throw in the occasional marketing
crap ???

It's hard to resist. This is a public forum, and as much as we'd like to be
providing 100% engineering data at all times, we also must try to sell our
products. I never post anything I believe is misleading, but I have (and
will continue to) actively direct people to our products and marketing
collateral whenever I feel it is relevant.

Last couple of years where plagued by bad economy. We saw
very few ASIC designs. A large factor why FPGA sales have
been growing is because they are getting big and fast enough
to be used in ASIC modeling and prototyping. I can't envision
a $1000 US FPGA going in to many designs. That are very
special situations - not the norm. In my opinion, FPGA are not
taking market share away from ASICS. Thats where Structured
ASICS and Gate Arrays come in.

Trust me, $1000 US FPGAs go into many designs. And we love it. The truth
is that as we push into smaller and smaller process technologies, the
investment in NRE costs such as masks, as well as development tools and the
engineering effort required to bring a chip out are increasing rapidly.
There are fewer and fewer sockets that have large enough revenues to
generate a high enough ROI on a (pure-play) ASIC development. Now,
comparing FPGAs at 90 nm against ASICs at 90 nm is not fair, since you can
get similar performance and cost at older technology nodes, but the trend is
still there.

Let's look at that $1000 FPGA again. Let's say it costs you $6 M to design,
test, and manufacture your first ASIC and $0 per unit thereafter, while the
FPGA costs $1M to develop & test, and $1000 per unit. You'd need to have
guarenteed volumes of more than 5000 units before this effort pays itself
off, and that's excluding the opportunity cost of tying up those resources
for the time it takes to develop the product. Including a desired ROI, it's
probably 10x higher. As the dev costs get higher, and FPGAs grow in density
but remain at the same price, the break-even point pushes further and
further out.

Examples of boxes with $1000 FPGAs in them: Think any big box that costs
~$100K -- routers, storage servers, telecom boxes, etc. There are companies
that have products that they are happy to sell 100 of each year. In these
markets, FPGAs are a perfect fit.

I agree that structured ASICs will also work to take market share from
ASICs, as they provide an intermediate solution in the cost-per-unit & fixed
cost space. That's why we have our HardCopy product line. This allows our
customers to go to production with an FPGA, with the insurance that they can
move to a structured ASIC in the future. Plus converting over is easy --
all the hard IP blocks are identical (PLLs, RAMs, etc.) reducing the chances
of problems in conversion. It's a hard-to-copy business strategy, and we
hope it will continue to a be a very succesful one.

And with the availability of low-cost, high-performance FPGAs such as
Cyclone, markets with volumes of 100,000+ units are now opening up to us.
Will we truely take a lot of market share from ASICs here? I dunno -- we'll
know the answer in five years after we've seen another full ASIC up-and-down
cyclone.

Regards,

Paul Leventis
Altera Corp.