XIL DCM Reset on XAPP462

[seyior]

Dear All: <p>I have tried the reset circuit for external feedback DCM on XAPP462 Figure 20. <p>Is it ok to use feedback clock input as the shift register to generate DCM reset? Modelsim's wave tell me that DCM will not output clock when it is at reset. <p>A miss for XAPP462 Figure 20? Or I made the misunderstanding. <p><a href="http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf">http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf</a> <p>regards, <BR>
seyior

 

[Steven K. Knapp]

This is indeed a mistake in the diagram in Figure 20. The clock feeding the
SRL16 should feed from the input clock (connected to CLKIN) and not from the
feedback clock (connected to CLKFB).

I will make sure that this is updated when we update XAPP462.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

&lt;seyior&gt; wrote in message news:ee83a9a.-1@WebX.sUN8CHnE...

Dear All:
I have tried the reset circuit for external feedback DCM on XAPP462 Figure
20.

Is it ok to use feedback clock input as the shift register to generate DCM
reset? Modelsim's wave tell me that DCM will not output clock when it is at

reset.

A miss for XAPP462 Figure 20? Or I made the misunderstanding.

http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf

regards,
seyior

 

[seyior]

Dear XILINX: <p> Thanks for the immediate help. I am happy to be a XILNX FPGA designer. <p>Regards, <BR>
seyior