XC9500 design does not fit into Coolrunner

K

Klaus Falser

Guest
Hello,

I have a rather large design for a XC95288XL which consumes 276 macrocells
of 288 possible.
Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
I tried to stuff the design into a Coolrunner II chip to look how it
would behave.

However, I was not able to make it fit even in a 512 macrocell device.
Timing should not be so tight, it has to run at 8 MHz clock, but the
timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

Can anybody which know's the XCR2 better than me give me a hit where
to pay attention?
How can I see from the report where the fitter has a problem?

Thanky you very much

--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it
 
Klaus Falser <kfalser@ihatespamdurst.it> wrote:
: Hello,

: I have a rather large design for a XC95288XL which consumes 276 macrocells
: of 288 possible.
: Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
: I tried to stuff the design into a Coolrunner II chip to look how it
: would behave.

Did you play with the fitter options?

: However, I was not able to make it fit even in a 512 macrocell device.
: Timing should not be so tight, it has to run at 8 MHz clock, but the
: timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

The Macrocell of the XC2 is not as wide as the cell of the XC95X(V), so some
logic may need expansion on two cells.

: Can anybody which know's the XCR2 better than me give me a hit where
: to pay attention?
: How can I see from the report where the fitter has a problem?

Did you look look at the *.rpt files?

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

=======================================================

Free software means: Contribute nothing, expect nothing

=======================================================
 
Have you considered other vendors?

Lattice makes several devices that will go beyond 512 Macrocells.
Also, their 5kve and XPLD family have 68-inputs into the macrocell blocks
which should make fitting easier.

Dan
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message
news:bpkjqf$7ug$1@news.tu-darmstadt.de...
Klaus Falser <kfalser@ihatespamdurst.it> wrote:
: Hello,

: I have a rather large design for a XC95288XL which consumes 276
macrocells
: of 288 possible.
: Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
: I tried to stuff the design into a Coolrunner II chip to look how it
: would behave.

Did you play with the fitter options?

: However, I was not able to make it fit even in a 512 macrocell device.
: Timing should not be so tight, it has to run at 8 MHz clock, but the
: timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

The Macrocell of the XC2 is not as wide as the cell of the XC95X(V), so
some
logic may need expansion on two cells.

: Can anybody which know's the XCR2 better than me give me a hit where
: to pay attention?
: How can I see from the report where the fitter has a problem?

Did you look look at the *.rpt files?

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

=======================================================

Free software means: Contribute nothing, expect nothing

=======================================================
 
In article <bpkjqf$7ug$1@news.tu-darmstadt.de>, bon@elektron.ikp.physik.tu-darmstadt.de
says...
Klaus Falser <kfalser@ihatespamdurst.it> wrote:
: Hello,

: I have a rather large design for a XC95288XL which consumes 276 macrocells
: of 288 possible.
: Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
: I tried to stuff the design into a Coolrunner II chip to look how it
: would behave.

Did you play with the fitter options?
There are not so many. You can choose between speed, density and balanced.
Something which improves fitting is to switch off "Keep hierarchy"
in the VHDL compiler options.

: However, I was not able to make it fit even in a 512 macrocell device.
: Timing should not be so tight, it has to run at 8 MHz clock, but the
: timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

The Macrocell of the XC2 is not as wide as the cell of the XC95X(V), so some
logic may need expansion on two cells.
This may be on of the reasons. But on the other side, not all equations are
so large and having twice as much macrocells should be more than enough.

: Can anybody which know's the XCR2 better than me give me a hit where
: to pay attention?
: How can I see from the report where the fitter has a problem?

Did you look look at the *.rpt files?
Sure I did. It is, however, at least a little bit difficult to scan 250 equations
to look for some anomaly. And I have got no idea how such an anomaly should look
like.

Thanks
--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it
 
Klaus Falser <kfalser@ihatespamdurst.it> wrote:

: Sure I did. It is, however, at least a little bit difficult to scan 250
: equations
: to look for some anomaly. And I have got no idea how such an anomaly
: should look like.
:
Try to understand what equations blew up. Strip down your code line by line
and see how the fitter behaves.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Try contacting the Xilinx hotline, they're usually willing to help
look at designs and can save you some time by at least identifying the
cause of the no-fit.
 
"Klaus Falser" <kfalser@IHATESPAMdurst.it> wrote in message
news:MPG.1a2d2836d298358b9896a0@151.99.250.3...
Did you look look at the *.rpt files?

Sure I did. It is, however, at least a little bit difficult to scan
250 equations
to look for some anomaly. And I have got no idea how such an anomaly
should look
like.
Klaus -

A couple of things you might try:

1. Compare the XC9500 reports to the CoolRunner reports.
2. Compile parts of the design by themselves, first to XC9500 then to
CoolRunner. See which modules blow up in the CoolRunner.

Robert
 
Klaus Falser wrote:
Hello,

I have a rather large design for a XC95288XL which consumes 276 macrocells
of 288 possible.
Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
I tried to stuff the design into a Coolrunner II chip to look how it
would behave.

However, I was not able to make it fit even in a 512 macrocell device.
Timing should not be so tight, it has to run at 8 MHz clock, but the
timing analyzer gives me 17-18 MHz on the slowest 10 ns device.

Can anybody which know's the XCR2 better than me give me a hit where
to pay attention?
How can I see from the report where the fitter has a problem?

Thanky you very much
Have you constrained the design (pin assignments, etc)? What
is the fitter complaining about?

There are some hard limits, like less OE lines than there are
outputs to a block. If, for instance, you are trying to create
a large GPIO device with more than 4 I/Os per block (8 are
possible) it won't work.

Kind regards,

Iwo
 
In article <3fc5e308$0$249$4d4ebb8e@read-nat.news.nl.uu.net>,
Iwo_dot_Mergler@soton_dot_sc_dot_philips_dot_com says...
Klaus Falser wrote:
Hello,
In article <3fc5e308$0$249$4d4ebb8e@read-nat.news.nl.uu.net>, you say...
Klaus Falser wrote:
Hello,

I have a rather large design for a XC95288XL which consumes 276 macrocells
of 288 possible.
Since Xilinx seems to prefer Coolrunner devices to the good old XC9500's
I tried to stuff the design into a Coolrunner II chip to look how it
would behave.
...snip .
Have you constrained the design (pin assignments, etc)? What
is the fitter complaining about?

There are some hard limits, like less OE lines than there are
outputs to a block. If, for instance, you are trying to create
a large GPIO device with more than 4 I/Os per block (8 are
possible) it won't work.

Kind regards,

Iwo
No, for my first try I did not give any constrains, whether for pins nor for the
timing.
The I/O interface is bus-like, so the I/O lines share all the same OE.
From my experience with the 9500's I have seen there are sometimes problems when
creating a too large multiplexor, which comes from the available Product terms per
macrocell.
For instance, if you have a bus and you want to read back from more
than 5 different registers, which implies a multiplexor before the output-pins,
you have to distribute your pins carefully, since every macrocell with an output pin
needs to steel PT from their neighbours.
Coolrunner CPLD seems to have less PT inputs per macrocells, but give enough
macrocells and without placing constraint I did expect some fit.

Best regards
--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it
 
"Klaus Falser" wrote
No, for my first try I did not give any constrains, whether for pins nor
for the
timing.
The I/O interface is bus-like, so the I/O lines share all the same OE.
From my experience with the 9500's I have seen there are sometimes
problems when
creating a too large multiplexor, which comes from the available Product
terms per
macrocell.
For instance, if you have a bus and you want to read back from more
than 5 different registers, which implies a multiplexor before the
output-pins,
you have to distribute your pins carefully, since every macrocell with an
output pin
needs to steel PT from their neighbours.
Coolrunner CPLD seems to have less PT inputs per macrocells, but give
enough
macrocells and without placing constraint I did expect some fit.
Comparing the two RPT files should give some guidelines ?.
It is common for fitters to give better info, for a design that fits, so
'approaching the problem from (just) below' can be much more productive.
When you have a partial design fitting, check the correct globals have
been mapped OK. Missing a global resource can balloon usage.
Sometimes the device package can have an influence - if there is more than
one
choice, get a report file for each package.
-jg
 

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