X & Y snap in grid control for tsmc18rf in cadence

[michael_skoufis]

Being new in this, I have a designed a chip using an arbitrary X & Y snap.
For this reason most likely my layout does not pass LVS (W & L mismatch by
10^(-6)%). Does anyone know what the appropriate snap is for this
technology?

Mike

 

[kentauta]

Hi Mike,

The minimum step size is defined in 0.USER GUIDE Part I of the design
rule in my design kit. Check the design rule documents in your design
kit.

Kentaro


michael_skoufis wrote:

Being new in this, I have a designed a chip using an arbitrary X & Y snap.
For this reason most likely my layout does not pass LVS (W & L mismatch by
10^(-6)%). Does anyone know what the appropriate snap is for this
technology?

Mike