X problem in gate simulation on registers without reset...

[wzhang]

Hi All,

I am running netlist simulation with ARM core in VCS. The ARM core
(gates) has some registers without reset. I find all those registers
and then use $deposit to set initial Q port value to either 1 or 0. My
question is if I deposit Q to all 0, simulation works fine but if I
deposit to random 1 and 0s, sometimes simulation fails. Anyone can
think of a scenario that random 1 and 0 will fail but all 0/1 pass?
Thanks!

 

[glen herrmannsfeldt]

wzhang <zhang.wenfang@gmail.com> wrote:

I am running netlist simulation with ARM core in VCS. The ARM core
(gates) has some registers without reset. I find all those registers
and then use $deposit to set initial Q port value to either 1 or 0. My
question is if I deposit Q to all 0, simulation works fine but if I
deposit to random 1 and 0s, sometimes simulation fails. Anyone can
think of a scenario that random 1 and 0 will fail but all 0/1 pass?

Without any more details, some state machines are sensitive
to the starting state. It is nice to design ones that can work
in any starting state, but that doesn't always happen.

-- glen

 

[hairyotter]

Hi,

it's not good.

If the designer put some non-reset flop it means that the circuit is
supposed to behave properly. You did a good thing to initialize them
with random values.

Before filing a case with ARM, one thing I would try is:
- do you have a wrong behaviour, or an x propagation ?

Since you're only $deposit'ing Q, there might be issues on D still
capturing an X in some cases ?

Instead of deposit, can you try force, keep the force active for a few
clock cycles just to ensure that the logic can propagate, then release
the forces before you remove the reset ?

Marco

On Apr 23, 10:06 pm, wzhang <zhang.wenf...@gmail.com> wrote:

Hi All,

I am running netlist simulation with ARM core in VCS. The ARM core
(gates) has some registers without reset. I find all those registers
and then use $deposit to set initial Q port value to either 1 or 0. My
question is if I deposit Q to all 0, simulation works fine but if I
deposit to random 1 and 0s, sometimes simulation fails. Anyone can
think of a scenario that random 1 and 0 will fail but all 0/1 pass?
Thanks!

 

[q-rious]

On Apr 23, 10:06 pm, wzhang <zhang.wenf...@gmail.com> wrote:

Hi All,

I am running netlist simulation with ARM core in VCS. The ARM core
(gates) has some registers without reset. I find all those registers
and then use $deposit to set initial Q port value to either 1 or 0. My
question is if I deposit Q to all 0, simulation works fine but if I
deposit to random 1 and 0s, sometimes simulation fails. Anyone can
think of a scenario that random 1 and 0 will fail but all 0/1 pass?
Thanks!

You have essentially hit the problem that one encounters when the
design 'has some registers without reset'. Many IPs make blatant
mistakes like this together with the assumptions in other part of
their own logic. You did the right thing in randomizing the values.
But also make sure the flops do not have an inherent 'reset' value
(such as D = some_signal & ~reset).

Whether you will get a quick response or not, do contact your IP
vendor for this.

--
Swapnajit
Project VeriPage:: SystemVerilog, PLI and PSL - all good stuffs.
http://www.project-veripage.com

 

[hairyotter]

I agree with you that this is a potential bad mistake.

However, I do not believe that ARM would make one like that, unless
you're using an alpha version of a brand new core.

However, I would be very interested in knowing the results of whzang
investigation

Marco.

You have essentially hit the problem that one encounters when the
design 'has some registers without reset'. Many IPs make blatant
mistakes like this together with the assumptions in other part of
their own logic. You did the right thing in randomizing the values.
But also make sure the flops do not have an inherent 'reset' value
(such as D = some_signal &  ~reset).

Whether you will get a quick response or not, do contact your IP
vendor for this.

--
Swapnajit
Project VeriPage:: SystemVerilog, PLI and PSL - all good stuffs.http://www.project-veripage.com