[WTF] Hierarchical designs and ATMELs CPLD fitters

[Johann Klammer]

I've been playing with atmels old stuff again...
I can not seem to get their fitter to accept hierarchical edif.
I am using the fitters from their WinCUPL download.

the commandline I am using:
wine fit1504 -ifmt EDIF -i a.edf -dev p1504c44 -JTAG=OFF

the input file:
http://members.aon.at/~aklamme4/scratch/afit/a.edf

I get:
[...]
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking INV_1 ...
Checking IVL_LPM_RE_XNOR_2_1 ...
Checking IVL_XNOR2 ...
Checking INV_1 ...
Checking IVL_LPM_RE_XNOR_2_1 ...
Checking IVL_XNOR2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking INV_1 ...
Checking IVL_LPM_RE_XNOR_2_1 ...
Checking IVL_XNOR2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking INV_1 ...
Checking INV_1 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking INV_1 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...
Checking IVL_LPM_RE_AND_2_1 ...
Checking IVL_AND2 ...

INTERNAL ERROR - Please contact your Hot-Line

The IVL_AND2 is the last instance inside the bldc module,
so the boo-boo seems to happen a bit later.
The message is awfully unspecific, tho'.

Strangely enough this one works:
http://members.aon.at/~aklamme4/scratch/afit/test.edf
(hand written to match aprim.lib from their old fit5_0.zip download)
But it only uses bottom level cells...

The edif files output by the fitters themselves(there's an option)
do not work, because the port names mismatch:
http://members.aon.at/~aklamme4/scratch/afit/ATF8255N.edn

I have also tried producing output files that match
atmel.std component library. but that gave the same results...
after editing atmel.std a that came with their wincupl installation,
as it seemed broken.
I got those messages:
``
Reading library ...
Warning : gate dff9 defined 24 times
Warning : gate dff5 defined 4 times
Warning : gate dff8f defined 4 times
``
(they have loads of identically named primitives in there...)

What do I have to do to to get a.edf to fit?
Does anybody spot an obvios mistek?

I've used icarus verilog to generate the edif file
the sources are there:
https://github.com/klammerj/iverilog/tree/master/tgt-atf15

The verilog file that was used to generate the edif:
https://raw.githubusercontent.com/klammerj/iverilog/master/tgt-atf15/v/bldc.v