wrong time delay in 1-bit arithmetic unit

I need some help on finding error in my verilog design.
I'm trying to build a 16-bit arithmetic unit by combining sixteen 1-
bit arithmetic units, but there is one problem I can't solve: time
delay doesn't match.
Here's the link to the overall explanation of the design I'm
implementing:
http://cyber.icu.ac.kr/platform/Common/Lecture/Lecture_Dataroom/c_down.asp?Gwamog_Cd=ICE1221B&SeqNo=1330023&Filename=Lab6_April-7_9_AU.pdf

I gave 2ns delay to XOR gates and 1ns to AND and OR gates.
According to the design, there should be 6ns delay to both the sum
output and carry-out of the 1-bit arithmetic unit, but i'm getting 6ns
delay for the sum output and 4ns delay for the carry-out.
Also, when testing the 16-bit arithmetic unit design, I found that the
carry-out of the 16th bit is stimulated when previous carry-outs are
not even stimulated yet.

I've looked over what I did more than 10times, but I couldn't find the
problem.

Here are my codes:

1. Y-Gen
`timescale 1ns/100ps

module YGen(b, sel, y);
input[1:0] sel; //select inputs
input b; //input
output y; //output
wire[3:0] i;

assign i= {1'b1, ~b, b, 1'b0};

MUX4 MUX4(sel, i, y);
endmodule


2. Full-Adder
`timescale 1ns/100ps

module fullAdder(a, b, cin, sum, cout);
input a, b, cin; //inputs
output sum, cout; //outputs
wire temp_sum, carry1, carry2;

xor #2 G1(temp_sum, a, b), G3(sum, cin, temp_sum);
and #1 G2(carry1, a, b), G4(carry2, temp_sum, cin);
or #1 G5(cout, carry1, carry2);
endmodule


3. 1-bit AU
module AU1(a, b, sel, cin, sum, cout);
input a, b, cin; // augend, addend, and carry-in
input[1:0] sel; //select inputs
output sum, cout; //sum and carry out
wire y;

YGen YGen(b, sel, y);
fullAdder fullAdder(a, y, cin, sum, cout);
endmodule


4. 16-bit AU
`timescale 1ns/100ps

module AU16(a, b, sel, cin, sum, cout, v);
input[15:0] a, b; //augend and addend bits
input[1:0] sel; //select inputs
input cin; //carry-in
output[15:0] sum, cout; //sum and carry-out
output v; //final carry-out and overflow

AU1 A0(a[0], b[0], sel, cin, sum[0], cout[0]), A1(a[1], b[1], sel,
cout[0], sum[1], cout[1]),
A2(a[2], b[2], sel, cout[1], sum[2], cout[2]), A3(a[3], b[3],
sel, cout[2], sum[3], cout[3]),
A4(a[4], b[4], sel, cout[3], sum[4], cout[4]), A5(a[5], b[5],
sel, cout[4], sum[5], cout[5]),
A6(a[6], b[6], sel, cout[5], sum[6], cout[6]), A7(a[7], b[7],
sel, cout[6], sum[7], cout[7]),
A8(a[8], b[8], sel, cout[7], sum[8], cout[8]), A9(a[9], b[9],
sel, cout[8], sum[9], cout[9]),
A10(a[10], b[10], sel, cout[9], sum[10], cout[10]),
A11(a[11], b[11], sel, cout[10], sum[11],
cout[11]),
A12(a[12], b[12], sel, cout[11], sum[12], cout[12]),
A13(a[13], b[13], sel, cout[12], sum[13],
cout[13]),
A14(a[14], b[14], sel, cout[13], sum[14], cout[14]),
A15(a[15], b[15], sel, cout[14], sum[15],
cout[15]);

xor #2 XOR(v, cout[14], cout[15]); //overflow detection
endmodule