Writing to stdout in VHDL

M

moshezsb

Guest
I am trying to write a debug message to stdout. It appears that the only
way
to do this is with the assert command.
So, in Verilog, I would type
$display ("mem[%d] = %d", i, mem);

In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;

Is this the only way to do this? Does textio only work on a file or can it
be used on stdout?
 
Hello,

the package textio defines the files:
INPUT
OUTPUT.

You can write to OUTPUT, which writes to stdout.

S.Netz
moshezsb wrote:
I am trying to write a debug message to stdout. It appears that the only
way
to do this is with the assert command.
So, in Verilog, I would type
$display ("mem[%d] = %d", i, mem);

In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;

Is this the only way to do this? Does textio only work on a file or can it
be used on stdout?
Click to expand...
 
Hi,
As Steffan noted, you do have STDOUT possibility using TEXTIO. You may
also want to try:

http://www.easics.com/webtools/freesics/PCK_FIO-2002.7

They have a neat printf like package. Also a google search for "printf vhdl
package" yielded:
bear.ces.cwru.edu/vhdl/source/debugio_h.vhd

HTH
Srinivasan

"moshezsb" <moshe-10@bezeqint.net> wrote in message
news:ec2a02d91c9e5f379763992b145c0557@localhost.talkaboutprogramming.com...
I am trying to write a debug message to stdout. It appears that the only
way
to do this is with the assert command.
So, in Verilog, I would type
$display ("mem[%d] = %d", i, mem);

In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;

Is this the only way to do this? Does textio only work on a file or can it
be used on stdout?
Click to expand...
 
Hello Steffen ,
Thank you very much for the quick answer.
regards,
Moshe.F
 
Hello Steffen,
Thank you for the Quick answer.
Regards,
Moshe.F
 
Hi Srinivasan,
Thank you for the quick answer.
Regards,
Moshe.F
 
"moshezsb" <moshe-10@bezeqint.net> wrote in message news:<ec2a02d91c9e5f379763992b145c0557@localhost.talkaboutprogramming.com>...

In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;

Is this the only way to do this?
Click to expand...

This would do the same thing:

report "mem("
& integer'image(i)
& ") = "
& integer'image(mem(i));

-- Mike Treseler
 
Hello.
Could you write sample with use package textio to write a debug message.

Now I'm use syntax: assert report ...... as Steffen Netz.

Thx
 
Hy Mariusz,

look at the example below.
Caution the first ( commented) form of the file declaration is vhdl93,
the second vhdl87!


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;

deassemble : PROCESS (trig)
-- FILE reportfile : text IS OUT "deassemble.ir";
FILE reportfile : text OPEN WRITE_MODE IS "deassemble.ir";

VARIABLE befehl: line;
BEGIN
IF trig'event AND trig = '1' AND trig'last_value = '0' THEN
IF dec = '1' THEN
write(befehl,now);
write(befehl,string'(" -> "));
hwrite(befehl,adr);
write(befehl,string'(" : "));
hwrite(befehl,ir);

writeline(REPORTFILE,befehl); -- writes to "deassemble.ir"
writeline(OUTPUT,befehl); -- writes to std_output
end if;
end process;

regard,
Steffen

Mariusz wrote:
Hello.
Could you write sample with use package textio to write a debug message.

Now I'm use syntax: assert report ...... as Steffen Netz.

Thx
Click to expand...
 
Hello.
Thx for sample code.
But i have problem with writes to "deassemble.ir"

In output window is next error
# Error: COMP96_0093: shft_reg.vhd : (69, 14): Actual parameter types in
subprogram call do not match subprogram formal parameter types.

I use first and second form file declaration .

Mariusz

Uzytkownik "Steffen Netz" <steffennetz@freenet.de> napisal w wiadomosci
news:20040922102210.5ed6d964@sund35...
Hy Mariusz,

look at the example below.
Caution the first ( commented) form of the file declaration is vhdl93,
the second vhdl87!


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;

deassemble : PROCESS (trig)
-- FILE reportfile : text IS OUT "deassemble.ir";
FILE reportfile : text OPEN WRITE_MODE IS "deassemble.ir";

VARIABLE befehl: line;
BEGIN
IF trig'event AND trig = '1' AND trig'last_value = '0' THEN
IF dec = '1' THEN
write(befehl,now);
write(befehl,string'(" -> "));
hwrite(befehl,adr);
write(befehl,string'(" : "));
hwrite(befehl,ir);

writeline(REPORTFILE,befehl); -- writes to "deassemble.ir"
writeline(OUTPUT,befehl); -- writes to std_output
end if;
end process;

regard,
Steffen

Mariusz wrote:
Hello.
Could you write sample with use package textio to write a debug
message.

Now I'm use syntax: assert report ...... as Steffen Netz.

Thx
Click to expand...
 
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