M
moshezsb
Guest
I am trying to write a debug message to stdout. It appears that the only
way
to do this is with the assert command.
So, in Verilog, I would type
$display ("mem[%d] = %d", i, mem);
In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;
Is this the only way to do this? Does textio only work on a file or can it
be used on stdout?
way
to do this is with the assert command.
So, in Verilog, I would type
$display ("mem[%d] = %d", i, mem);
In VHDL I get something like
assert (1=0) report "mem[" & integer'image(i) & "] = " &
integer'image(mem)) severity note;
Is this the only way to do this? Does textio only work on a file or can it
be used on stdout?