writing synthesizable while loops

[Ani]

hi

i understand that it is not possible to have variable loop limit in a
while loop for synthesis. However, my application requires that i run
the loop a variable number of times depending on the input. what is
the way out?

thanx
aniruddha

 

[Jonathan Bromley]

On 1 Feb 2007 02:05:57 -0800, "Ani" <aniruddha.udipi@gmail.com> wrote:

i understand that it is not possible to have variable loop limit in a
while loop for synthesis. However, my application requires that i run
the loop a variable number of times depending on the input. what is
the way out?

State machine.
--
Jonathan Bromley, Consultant

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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[John_H]

Ani wrote:

hi

i understand that it is not possible to have variable loop limit in a
while loop for synthesis. However, my application requires that i run
the loop a variable number of times depending on the input. what is
the way out?

thanx
aniruddha

Consider what people did before the "while" statement was available in
programming; it hasn't always been there.

 

[Andy]

On Feb 1, 4:05 am, "Ani" <aniruddha.ud...@gmail.com> wrote:

hi

i understand that it is not possible to have variable loop limit in a
while loop for synthesis. However, my application requires that i run
the loop a variable number of times depending on the input. what is
the way out?

thanx
aniruddha

HDL loops are unrolled prior to synthesis, so they must have a static
bound. You can have an early exit within the loop, so you could set
the loop bounds as large as you might need, and then conditionally
exit the loop when appropriate. Beware that hardware will be generated
for the entire unrolled loop, which may not be practical.

Otherwise, as said previously, you're looking at a state machine
design.

Andy

 

[Ani]

On Feb 1, 9:18 pm, "Andy" <jonesa...@comcast.net> wrote:

On Feb 1, 4:05 am, "Ani" <aniruddha.ud...@gmail.com> wrote:

hi

i understand that it is not possible to have variablelooplimit in a
whileloopfor synthesis. However, my application requires that i run
theloopa variable number of times depending on the input. what is
the way out?

thanx
aniruddha

HDL loops are unrolled prior to synthesis, so they must have a static
bound. You can have an early exit within theloop, so you could set
theloopbounds as large as you might need, and then conditionally
exit theloopwhen appropriate. Beware that hardware will be generated
for the entire unrolledloop, which may not be practical.

Otherwise, as said previously, you're looking at a state machinedesign.

Andy

Hi,

Can somebody give me an example of a simple while loop in verilog and
the corresponding state machine used to achieve the same result with
synthesizable code? I want to have a variable loop limit...

thanx

aniruddha