writing RTL in veriloga

[DReynolds]

I am working on a mixed signal chip that is mostly analog and my
question is about modeling and simulating the digital. Has anyone
written their RTL in veriloga? If so, what are the pluses and minuses?
I have modeled counters and such and have not found any problems in
generating the functionality I need in veriloga but I have not tried
writing an FSM...

I realize that with AMS I can run verilog, but most of the time I don't
have access to the license, so I am looking an alternative.

David

 

[Andrew Beckett]

On 26 Oct 2006 05:35:49 -0700, "DReynolds" <spurwinktech@gmail.com> wrote:

I am working on a mixed signal chip that is mostly analog and my
question is about modeling and simulating the digital. Has anyone
written their RTL in veriloga? If so, what are the pluses and minuses?
I have modeled counters and such and have not found any problems in
generating the functionality I need in veriloga but I have not tried
writing an FSM...

I realize that with AMS I can run verilog, but most of the time I don't
have access to the license, so I am looking an alternative.

David

Well, you can do it, but it's only really practical for relatively small amounts
of logic, since you're treating all your logic nets as electrical. You need to
make sure you model transitions properly in the models to avoid (excessively)
discontinuous behaviour...

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.