Writing a Verilog A model.

Guest
Dear all,

I have working experience with Verilog and I am new to this
Verilog-A. For my Project reasons I have to write a Verilog-A model to
analyze glitches. I need some thing to read before i can start working
on Verilog-A. Can any one of you suggest some reading material
preferably online.

Thanks and Regards,
kamesh.
 
Hi again,

I have doen a bit of searching in the previous posts...and found
that cdsdoc is an amazing resource. I have printed it out and will be
having a glance now.

Thanks,
kamesh.
 
The official on-line site is :
http://www.eda.org/verilog-ams with examples

There is also an interesting web site : www.designers-guide.com
where lots of information about Verilog-A and Verilog-AMS are
available, with examples coding style, books references, etc ...

================
Kholdoun TORKI
http://cmp.imag.fr
================

vkamesh@gmail.com wrote:

Dear all,

I have working experience with Verilog and I am new to this
Verilog-A. For my Project reasons I have to write a Verilog-A model to
analyze glitches. I need some thing to read before i can start working
on Verilog-A. Can any one of you suggest some reading material
preferably online.

Thanks and Regards,
kamesh.
Click to expand...
 
Hi Kamesh,

Verilog-AMS Language Reference Manual version 2.2 has been recently
approved (Accellera standard), you can download a copy at

http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.2/AMS-LRM-2-2.pdf

Cheers,
Prasanna
 
Thanks a lot Torki and Prasanna.. I will take a look at the websites
you have suggested.

Thank you oneca again,
kamesh.
 
Hi all,

After reading the suggested material by Torki and Prasanna, a new
doubt has arisen in my mind.

What is the difference between Verilog-A and Verilog-AMS ? Are both one
and the same ? I have already take the printout on Verilog-A from
cdsdoc. Can any one please elabore on this. I am new to this analog
field.

I need to analyze glitches in my circuit and was planning to write a
model in verilog-A. I have stopped working temporarily because i
urgently needed this clarification.

Thanks in advance,
kamesh.
 
Hi Kamesh,

Verilog-A was an OVI standard to represent analog only systems.
Verilog-AMS is a super set of
- Verilog-A
- Verilog-D (1364-1995) plus
- Mixed signal extensions

With Veriog-AMS you can have initial, always and analog blocks all in
one module. One can also instantiate SPICE devices (like resistors and
capacitors) in the same module. These mixed-signal blocks provide the
ability to access data and be controlled by events from the other
domain. In addition to providing mixed-signal interaction directly
through behavioral descriptions, Verilog-AMS HDL also provides a
mechanism for the mixed-signal interaction between modules. I suggest
you read section 1.1 "overview" and 8.1 "Mixed signal" at least to
start with to gain understanding of AMS and cross domain interactions.

Cheers,
Prasanna
 
On 7 Mar 2005 21:31:56 -0800, "Prasanna" <pratam@gmail.com> wrote:

Hi Kamesh,

Verilog-A was an OVI standard to represent analog only systems.
Verilog-AMS is a super set of
- Verilog-A
- Verilog-D (1364-1995) plus
- Mixed signal extensions

With Veriog-AMS you can have initial, always and analog blocks all in
one module. One can also instantiate SPICE devices (like resistors and
capacitors) in the same module. These mixed-signal blocks provide the
ability to access data and be controlled by events from the other
domain. In addition to providing mixed-signal interaction directly
through behavioral descriptions, Verilog-AMS HDL also provides a
mechanism for the mixed-signal interaction between modules. I suggest
you read section 1.1 "overview" and 8.1 "Mixed signal" at least to
start with to gain understanding of AMS and cross domain interactions.

Cheers,
Prasanna
Click to expand...
Kamesh,

You might also want to read a copy of "A Designer's Guide to Verilog-AMS"
http://www.designers-guide.org/Books/#Kundert-2004

Andrew.
 
Thanks a lot prasanna and Andrew. your explantions were very helpul.
Now i can peacefully write my models.

Best Regards,
Kamesh.
 
Hi once again,

my doubts does not seem to end.

I am using cadence 4.4.6 . I am not sure whether the spectreS simulator
in here supports verilogA or verilog AMS. Can any one give me a clue.

Thanks in advance,
kamesh.
 
and by the way iam using cadence's msfb (mixed signal front to back).
So i suppose it has to simulate verilog A and verilog AMS. not sure
about this though. Would be great if some one could point me in the
right direction.

Thanks and regards,
kamesh.
 
On 9 Mar 2005 08:49:06 -0800, vkamesh@gmail.com wrote:

Hi once again,

my doubts does not seem to end.

I am using cadence 4.4.6 . I am not sure whether the spectreS simulator
in here supports verilogA or verilog AMS. Can any one give me a clue.

Thanks in advance,
kamesh.
Click to expand...
spectreS supports Verilog-A. The simulator is still spectre, even when using
spectreS (the difference is the interface - do a google search on spectreS
and I'm sure you'll find some posts outlining the difference).

Since spectre supports Verilog-A, it will do so regardless of the interface
to the simulator being used.

Andrew.
 
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