writing a testbench

[Smith]

Hi all.
I'm now having doubt in my process of writing a testbench.
In the module to be tested, there is function block which contains the
inputs come from the main module. I wonder that do I need to include
all the inputs listed in the function block into my testbench or just
need to included the inputs and output sin the main module block?

Thanks advanced for everyone help.

 

[ngsayjoe@gmail.com]

Can you show some examples for what you mean?

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com


Smith wrote:

Hi all.
I'm now having doubt in my process of writing a testbench.
In the module to be tested, there is function block which contains the
inputs come from the main module. I wonder that do I need to include
all the inputs listed in the function block into my testbench or just
need to included the inputs and output sin the main module block?

Thanks advanced for everyone help.

 

[Smith]

hi,
here is a part of my coding where the lower portion of the coding is
the function block which its inputs are from the output of the main
module as declared in the upper portion of the coding.

I'm not sure whether the inputs listed in the function block should be
included in the declaration of ports in my testbench.

Thanks advanced.
_________________________________________________________

module proj2 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 16;
parameter BCD_DIGITS_OUT_PP = 5;
parameter BIT_COUNT_WIDTH_PP = 4;

// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // initiates a conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // indicates conversion is done

reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;

// Internal signal declarations

reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;

//--------------------------------------------------------------------------
// Functions & Tasks
//--------------------------------------------------------------------------

function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
_________________________________________________________
Smith wrote:

Hi all.
I'm now having doubt in my process of writing a testbench.
In the module to be tested, there is function block which contains the
inputs come from the main module. I wonder that do I need to include
all the inputs listed in the function block into my testbench or just
need to included the inputs and output sin the main module block?

Thanks advanced for everyone help.

 

[ngsayjoe@gmail.com]

Hi Smith,

Now, I get what you mean. The answer is "no", port declarations of a
function aren't required to be declared again in the module. Thanks.

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Smith wrote:

hi,
here is a part of my coding where the lower portion of the coding is
the function block which its inputs are from the output of the main
module as declared in the upper portion of the coding.

I'm not sure whether the inputs listed in the function block should be
included in the declaration of ports in my testbench.

Thanks advanced.
_________________________________________________________

module proj2 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 16;
parameter BCD_DIGITS_OUT_PP = 5;
parameter BIT_COUNT_WIDTH_PP = 4;

// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // initiates a conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // indicates conversion is done

reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;

// Internal signal declarations

reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;

//--------------------------------------------------------------------------
// Functions & Tasks
//--------------------------------------------------------------------------

function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
_________________________________________________________
Smith wrote:
Hi all.
I'm now having doubt in my process of writing a testbench.
In the module to be tested, there is function block which contains the
inputs come from the main module. I wonder that do I need to include
all the inputs listed in the function block into my testbench or just
need to included the inputs and output sin the main module block?

Thanks advanced for everyone help.