write signals at different processes

[default]

I'm gonna write some signal from different processes. The signal(register)
is increased under some clock(synchrnous process), if the clock is disabled,
the signal will be written in another process(asynchrnous process and it
controls the clock enable). But it couldn't work. How to solve this problem?
Thanks much. ding

 

[Bhattiprolu RaviKumar]

If you try to write to a signal from different processes it creates
multiple drivers and it makes the signal UNKNOWN. So, you need to
remove one driver before activating the other. The foolwoing is a
example code which allows two different processes to write on same
signal.
architecture test of myent is
SIGNAL outSig : std_logic;
begin
p1: process (CLK)
begin
if (CLKEN = '0') then
outSig <= 'Z' ; --disable driver
else
--other code
end if;
end process;

p2: process (CLKEN, in2) then
if (CLKEN = '1') then
outSig <= ' Z' ; -- disable driver and allow p1 to
write
else
outSig <= '1'; -- write whatever is the required value
end if
end process;
end test;

Hope this Helps
regards,
ravi
"default" <default@uccs.edu> wrote in message
news:3f94859d$1@darkstar...

I'm gonna write some signal from different processes. The
signal(register)
is increased under some clock(synchrnous process), if the clock is
disabled,
the signal will be written in another process(asynchrnous process
and it
controls the clock enable). But it couldn't work. How to solve this
problem?
Thanks much. ding

 

[Thomas Stanka]

"default" <default@uccs.edu> wrote:

I'm gonna write some signal from different processes. The signal(register)
is increased under some clock(synchrnous process), if the clock is disabled,
the signal will be written in another process(asynchrnous process and it
controls the clock enable). But it couldn't work. How to solve this problem?

How about generating an internal counter clock using an external
counter clock and the asynch enable. And a process using that
generated internal clock for a counter.

I asume you have either a sync clock or a asynch clock (step signal or
whatever)
and like the counter to increase its value for each rising edge on one
of the both signals but could stand if sometimes the counter waits
until falling edge instead of a risign edge as long as now pulse is
ignored after all.

clk_int<=sync_clk XOR async_clk;

process (clk_int, Rst)
if Rst....
Counter<=0;
elsif rising_edge(clk_int)
Counter>counter+1;
end if;

bye Thomas

 

[Shaomin]

Thanks very much.

My idea is:
I attempted to finish that in one process and simulated successfully,
but it couldn't be synthesized. So I had to implemented in two processes.

The clocked counter could be read/written in another asyn process. Under
your driver logic(tristate), the counter value could not get value from
other process. So I am gonna use two signals to implement it.

how do you think so? Thanks much.

shaomin

Bhattiprolu RaviKumar wrote:

If you try to write to a signal from different processes it creates
multiple drivers and it makes the signal UNKNOWN. So, you need to
remove one driver before activating the other. The foolwoing is a
example code which allows two different processes to write on same
signal.
architecture test of myent is
SIGNAL outSig : std_logic;
begin
p1: process (CLK)
begin
if (CLKEN = '0') then
outSig <= 'Z' ; --disable driver
else
--other code
end if;
end process;

p2: process (CLKEN, in2) then
if (CLKEN = '1') then
outSig <= ' Z' ; -- disable driver and allow p1 to
write
else
outSig <= '1'; -- write whatever is the required value
end if
end process;
end test;

Hope this Helps
regards,
ravi
"default" <default@uccs.edu> wrote in message
news:3f94859d$1@darkstar...

I'm gonna write some signal from different processes. The

signal(register)

is increased under some clock(synchrnous process), if the clock is

disabled,

the signal will be written in another process(asynchrnous process

and it

controls the clock enable). But it couldn't work. How to solve this

problem?

Thanks much. ding