WISHBONE read cycle VHDL implementation

[Edmond Cote]

Hi,

Supposing I have a Wishbone compatible (or other) SLAVE device (such as
memory) which does not necessairly return data within a single clock cycle,
what would the best possible implementation be with regards to which signals
need to be latched, the type of state machine to use, how can a stall signal
(wait state) be generated, etc..

For example, consider a very simplistic read implementation (ie. how can
I make this better), is there any public implementations or other
documentation that I can follow?

-- WISHBONE input signals
ack_i : in std_logic;
dat_i : in std_logic_vector(31 downto 0);

-- WISHBONE output signals
stb_o : out std_logic;
we_o : out std_logic;
adr_o : out std_logic_vector(31 downto 0);
dat_o : out std_logic_vector(31 downto 0);
....
we_o <= '0' -- always reading
stb_o <= a and b or c; -- some condition
adr_o <= x"1101011" --always the same address

process(ack_i)
if ack_i = '1' then
stb_o <= 0
dat <= dat_i; -- am I to assume that this will latch the data in,
what do I do about input data for writing, do I need to latch that?
end
end process


nb. I guess this wouldn't conform to the specification, since this is
clearly not synchronous. (pg 102 of the manual).


Thanks in advance!

-Ed