P
Preben Holm
Guest
Hi everyone
We're are a couple guys having quite some trouble with some VHDL-stuff.
It doesn't work as expected.
Our system consist of a viewer (master: leds), a manipulator (master,
not coded yet), a grabber (master: fill-mem (just "fill's" memory)) and
a memory-controller (slave: memory).
We have connected these with a wishbone compatible bus created with the
"WISHBONE builder" downloadet from opencores.org.
This probably works as it should (quite a lot code).
We connect our modules in the file "wb_sys.vhd".
Our two masters are located in "fill_mem.vhd" and "leds.vhd"
The memory manager is located in "memory.vhd"
The task of memory.vhd is to interface the SRAM (at the spartan 3
starter kit from xilinx/digilent) and control sending ACK's and keep
head of timing.
The task of leds.vhd is to display the contents of the RAM with a nice
interval (readable for the human eye)
For now it is simplified as reading one address (0x4)
The task of fill-mem.vhd is to fill the memory with different content.
For now it is simplified as filling one address (0x0) with a pattern
("01010101010101010101010110" or something like this)
The problem is, that the leds at the spartan kit shows the content of
the 0x0-address instead of the 0x4 address.
We can't find the error.. It seems like the data-bus in the interconnect
is remembered and the slave not selected at all. But I have no idea of
how to find this error.
The project is made with ISE 7.1-04 and can be found at my website:
http://www.interrupt.dk/WB_MEM2LEDS.rar
Thanks for helping us out.
/ Preben
We're are a couple guys having quite some trouble with some VHDL-stuff.
It doesn't work as expected.
Our system consist of a viewer (master: leds), a manipulator (master,
not coded yet), a grabber (master: fill-mem (just "fill's" memory)) and
a memory-controller (slave: memory).
We have connected these with a wishbone compatible bus created with the
"WISHBONE builder" downloadet from opencores.org.
This probably works as it should (quite a lot code).
We connect our modules in the file "wb_sys.vhd".
Our two masters are located in "fill_mem.vhd" and "leds.vhd"
The memory manager is located in "memory.vhd"
The task of memory.vhd is to interface the SRAM (at the spartan 3
starter kit from xilinx/digilent) and control sending ACK's and keep
head of timing.
The task of leds.vhd is to display the contents of the RAM with a nice
interval (readable for the human eye)
For now it is simplified as reading one address (0x4)
The task of fill-mem.vhd is to fill the memory with different content.
For now it is simplified as filling one address (0x0) with a pattern
("01010101010101010101010110" or something like this)
The problem is, that the leds at the spartan kit shows the content of
the 0x0-address instead of the 0x4 address.
We can't find the error.. It seems like the data-bus in the interconnect
is remembered and the slave not selected at all. But I have no idea of
how to find this error.
The project is made with ISE 7.1-04 and can be found at my website:
http://www.interrupt.dk/WB_MEM2LEDS.rar
Thanks for helping us out.
/ Preben