wishbone core with ethernet, hierarchy / architecture

Hello,
I am pretty new to working with FPGAs and verilog in general but have a
decent knowledge of programming, and Im trying to grasp the whole
concept of working with the wishbone, as well as verilog architecture.
I have the wishbone commax core and the ethernet ip core from
opencores.org, and im wondering how to go about setting up a basic
system to have some ethernet communication coming from my board which
currently is a Virtex-4 board , with a PHY chip built onto it. I know
the cores themselves already have a great setup, but im still unclear
on how to just place it all together. Im going to keep trying to play
around with it more and dig around more to see exactly how to do this,
but im the meaintime some sort of basic example of how to go about
setting it up would be greatly appreciated. Im not looking for code as
much as im looking for just a genereal layout of the hierarchy that I
could use in ISE (which im using for programming atm).

Thank you for your time,
Weizbox

 

[Jason Zheng]

mwiesbock@gmail.com wrote:

Hello,
I am pretty new to working with FPGAs and verilog in general but have a
decent knowledge of programming, and Im trying to grasp the whole
concept of working with the wishbone, as well as verilog architecture.
I have the wishbone commax core and the ethernet ip core from
opencores.org, and im wondering how to go about setting up a basic
system to have some ethernet communication coming from my board which
currently is a Virtex-4 board , with a PHY chip built onto it. I know
the cores themselves already have a great setup, but im still unclear
on how to just place it all together. Im going to keep trying to play
around with it more and dig around more to see exactly how to do this,
but im the meaintime some sort of basic example of how to go about
setting it up would be greatly appreciated. Im not looking for code as
much as im looking for just a genereal layout of the hierarchy that I
could use in ISE (which im using for programming atm).

Thank you for your time,
Weizbox

I'm not quite familiar with wishbone's interconnects (they are quite

flexible with different kinds of connection). But with any system
design, you need to think about what devices that you need to put on the
bus, how fast the bus will be running, and bandwidth issues. ISE works
with source files, so you probably need to provide a module to connect
all the devices together on the bus (eth core, cpu, other I/O). Xilinx
has another software called EDK that's specifically used for SoC
development, but they use Xilinx's standard bus, not wishbone.

To get broader response, I think you will be better off asking this
question on comp.arch.fpga as well.

-jz

 

Thank you jz,
It's probably a good idea as well to post it in comp.arch.fpga, since
it isnt specificly verilog, and I do need more of a basic idea as far
as hooking everyhting up, moreso when it comes to designing with ISE,
which is somewhat new to me as well.

Thanks again, Ill try the repost,
-Weizbox