A
Anand P. Paralkar
Guest
During synthesis and pre layout timing analysis, we assume a certain
wire load model for the interconnect for delay estimates.
Queries:
1. Is only the wire load model *type* assumed or are there any
assumptions made on the *lengths* of interconnects too.
2. Does the synthesis tool and STA tool influence the placement
and layout (because of the delay estimates) in any way.
I am trying to figure out how zero timing violations in synthesis and
STA is sufficient to *guarantee* that there will not be any timing
violations during PAR.
Thanks,
Anand
wire load model for the interconnect for delay estimates.
Queries:
1. Is only the wire load model *type* assumed or are there any
assumptions made on the *lengths* of interconnects too.
2. Does the synthesis tool and STA tool influence the placement
and layout (because of the delay estimates) in any way.
I am trying to figure out how zero timing violations in synthesis and
STA is sufficient to *guarantee* that there will not be any timing
violations during PAR.
Thanks,
Anand