wire assigns

[T. Irmen]

Hi,

is it possible and standard compliant to use a "assign" statement to assign
wires?

wire [17:0] wire_1
wire [17:0] wire_2

assign wire_1 = wire_2

Thank you for all comments!

thomas

 

[Allan Herriman]

On Fri, 7 May 2004 09:58:35 +0200, "T. Irmen" <tirmen@gmx.net> wrote:

Hi,

is it possible and standard compliant to use a "assign" statement to assign
wires?

wire [17:0] wire_1
wire [17:0] wire_2

assign wire_1 = wire_2

Some semicolons might help:

wire [17:0] wire_1;
wire [17:0] wire_2;

assign wire_1 = wire_2;

is perfectly valid, as is:

wire [17:0] wire_2;
wire [17:0] wire_1 = wire_2;

Regards,
Allan.

 

[T. Irmen]

Hi Allan,

sure the semicolons ;-)

Are you sure that this assigns

assign wire_1 = wire_2;

wire [17:0] wire_2;
wire [17:0] wire_1 = wire_2;

are absolutly equivalent?

At a other point of view, the assign syntax says:
assign #{delay} net_name = expression;

and expression could be 1? wire_2: dummy;

So that this assign should be the same also.

Does the wire assign implicit some directions?

kind regards,
thomas




"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> schrieb im
Newsbeitrag news:djgm90hkrjdgd87oq9j0cebe3traf1hkdf@4ax.com...

On Fri, 7 May 2004 09:58:35 +0200, "T. Irmen" <tirmen@gmx.net> wrote:

Hi,

is it possible and standard compliant to use a "assign" statement to
assign
wires?

wire [17:0] wire_1
wire [17:0] wire_2

assign wire_1 = wire_2

Some semicolons might help:

wire [17:0] wire_1;
wire [17:0] wire_2;

assign wire_1 = wire_2;

is perfectly valid, as is:

wire [17:0] wire_2;
wire [17:0] wire_1 = wire_2;

Regards,
Allan.

 

[Steven Sharp]

"T. Irmen" <tirmen@gmx.net> wrote in message news:<c7ffjc$2tm$1@nets3.rz.RWTH-Aachen.DE>...

Hi,

is it possible and standard compliant to use a "assign" statement to assign
wires?

wire [17:0] wire_1
wire [17:0] wire_2

assign wire_1 = wire_2

Of course. The right-hand-side of a continuous assignment is an expression.
An identifier is a legal expression. A constant would also be a legal
expression. They are just particularly simple expressions. You seem to be
assuming that an expression has to have operators in it, but it doesn't.

 

[T. Irmen]

Hi Steven,

okay. Does these assignments have a direction in meaning of wire2 drives
wire1, or is it bidirectional?

Thank you in advance,
thomas

 

[Steven Sharp]

"T. Irmen" <tirmen@gmx.net> wrote in message news:<c7oilg$cnh$1@online.de>...

okay. Does these assignments have a direction in meaning of wire2 drives
wire1, or is it bidirectional?

By the language definition, it is unidirectional. A continuous assignment
drives the left-hand-side with the value on the right-hand-side. It has
no effect on anything on the right-hand-side, and other drivers of the
net on the left-hand-side will not affect the right-hand-side. It acts
much like a buffer (except that it can pass a Z value).

However, a synthesis tool will probably treat this simple case specially,
and just short the two nets together to make them the same net. This
will create a bidirectional connection, which means that the behavior of
the post-synthesis design will not exactly match the pre-synthesis design.
The output of synthesis may only approximate the RTL input.