Guest
Hi
I described asynchronous memory (32bit wide, 2048 depth) like below,
and the behavior is not correct. The point of problem is shown below,,,
When we change into
DO <= RAM(CONV_INTEGER(address));
the behavior is okay......while I don't know exactly why
Thankyou for reading and help...
-------------------------------------------------
entity mem is
port( ce: in std_logic;
rw: in std_logic; -- read(0), write(1)
address: in std_logic_vector(31 downto 0);
DI: in std_logic_vector(31 downto 0);
DO: out std_logic_vector(31 downto 0));
end mem;
architecture arch of mem is
-- 32-bit words, word-addressable memory
constant depth : integer := 2048;
type mem1 is array (0 to depth) of reg32; -- 32 bit word
signal RAM : mem1;
signal adA_temp: reg32; -- temporaray signal
begin
-- ASYNCHRONOUS write
process(ce, rw, address)
begin
if ce='1' and rw='1' then
RAM(CONV_INTEGER(address)) <= DI;
end if;
end if;
end process;
-- ASYNCHRONOUS reading
process(ce, rw, address)
begin
if ce='1' and rw='0' then
adA_temp <= address; ----**** problem
DO <= RAM(CONV_INTEGER(adA_temp));
-- ** DO <= RAM(CONV_INTEGER(address));
end if;
end process;
end arch;
I described asynchronous memory (32bit wide, 2048 depth) like below,
and the behavior is not correct. The point of problem is shown below,,,
When we change into
DO <= RAM(CONV_INTEGER(address));
the behavior is okay......while I don't know exactly why
Thankyou for reading and help...
-------------------------------------------------
entity mem is
port( ce: in std_logic;
rw: in std_logic; -- read(0), write(1)
address: in std_logic_vector(31 downto 0);
DI: in std_logic_vector(31 downto 0);
DO: out std_logic_vector(31 downto 0));
end mem;
architecture arch of mem is
-- 32-bit words, word-addressable memory
constant depth : integer := 2048;
type mem1 is array (0 to depth) of reg32; -- 32 bit word
signal RAM : mem1;
signal adA_temp: reg32; -- temporaray signal
begin
-- ASYNCHRONOUS write
process(ce, rw, address)
begin
if ce='1' and rw='1' then
RAM(CONV_INTEGER(address)) <= DI;
end if;
end if;
end process;
-- ASYNCHRONOUS reading
process(ce, rw, address)
begin
if ce='1' and rw='0' then
adA_temp <= address; ----**** problem
DO <= RAM(CONV_INTEGER(adA_temp));
-- ** DO <= RAM(CONV_INTEGER(address));
end if;
end process;
end arch;