widthof()

[DW]

is there such a facility in Verilog? it would be nice if there was.

 

[Steven Sharp]

Stephen Williams <spamtrap@icarus.com> wrote in message news:<40D84925.4000809@icarus.com>...

Icarus Verilog implements $bits(), which is like sizeof() in C.
This is copied from SystemVerilog. So far as I can tell, the
IEEE1364 ETF has not adopted this feature.

The archives indicate that something like this was proposed for
Verilog-2001, but was rejected. I was not a member at that time,
so I don't know the reasoning.

Even though Icarus Verilog handles it specially, it is possible
to write a PLI function that implements $bits.

A basic implementation like this is indeed pretty straightforward.
However, I suspect the most likely place for it to be desired is
in contexts that require constant expressions. Since system
functions are not allowed in constant expressions, this wouldn't
work. Allowing this in constant expressions would require an
implementation to handle some very messy dependencies during
parameter value propagation during elaboration.

 

[Stephen Williams]

DW wrote:

is there such a facility in Verilog? it would be nice if there was.

Icarus Verilog implements $bits(), which is like sizeof() in C.
This is copied from SystemVerilog. So far as I can tell, the
IEEE1364 ETF has not adopted this feature.

Even though Icarus Verilog handles it specially, it is possible
to write a PLI function that implements $bits.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Steven Sharp]

"DW" <dave_wooff@hotmail.com> wrote in message news:<cb9ch6$rfn$1$830fa79d@news.demon.co.uk>...

is there such a facility in Verilog? it would be nice if there was.

I believe that VHDL needs something like this because it has features
like unconstrained arrays.

In Verilog, any object has been declared with a static width using
constant expressions, and those same constant expressions can be
used wherever you wanted the width. I.e. if you declared

wire [WIDTH-1:0] w;

clearly the width is just WIDTH. Since you provided the values for
the declaration, you have them for any other purpose that needs the
width. It might be slightly more convenient to have a widthof() in
some situations, but it isn't actually needed.

With SystemVerilog will come the ability to declare vectors that
are made up of sub-fields like a structure. In this case, it becomes
awkward to add up the widths of all the sub-fields yourself. A type
may also come from a typedef defined somewhere else, and you would
like to keep the definition somewhat opaque. In these situations,
a way of getting the width becomes more important.