Why wouldn't this infer a flop with async reset and sync ena

[fpgabuilder]

Hi Folks,

Both Precision Synthesis and Altera Quartus 2.0 cannot infer flops with
async reset and enable in the following code. I have checked that the
nclk and nrst_n are properly connected to the module.

What am I missing?

TIA,
Sanjay

-------

reg [23:0] irq_event_reg [0:1];

always@(posedge nclk or negedge nrst_n)
begin : irq_event_reg_sync
if(!nrst_n)
begin
irq_event_reg[0] <= 24'd0;
irq_event_reg[1] <= 24'd0;
end
else
begin
irq_event_reg[0] <= nwd;
irq_event_reg[1] <= irq_event_reg[0][23:0];
end
end

assign irq_event[23:0] = irq_event_reg[1][23:0];

 

[fpgabuilder]

Sorry, In this particular case, the sync enable is not present. I
forgot to notice that I had edited that part as a test. In anycase,
enable or no enable, the synthesizer complains that it cannot infer a
flop.

-sanjay

 

[Chris F Clark]

Just a guess, but what if you make two regs rather than a reg array
(memory) with two elements. It's isn't uncommon for compilers to
treat arrays only as a unit and not as individual elements, even when
the elements are always referenced by constant subscripts.

Hope this helps,
-Chris

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[fpgabuilder]

Looks like your theory is correct Chris.
Thanks.
-sanjay