Why won't Xilinx document their code??

[lecroy]

If I look at your latest unisim_vital.vhd and the previous version of
the file, there have been some major changes that effected my
simulation. Interesting, once again the headers did not change. They
still show the file not being updated after 1996, ending with change
86.

I brought this up with the models in the past.

Is there a reason that you don't want to take the time to document
your work?

 

[Ray Andraka]

Probably in a related vein, Xilinx has removed the TimingChecksOn generic
from the clocked elements in the unisim library. Not a problem if you
never touched it, however the default value had been true, which created
some delta clock delay problems with mixed instantiated/inferred designs
a while back. As a result, my library, and I'm sure others has elements
with these primitives with the TimingChecksOn generic set to false. Now
with the new unisim library, it is completely gone, so any old code has
to be revised to be able to compile. Would have been much cleaner to
just leave the generic there as a dummy, even if it has no references in
the component.

lecroy wrote:

If I look at your latest unisim_vital.vhd and the previous version of
the file, there have been some major changes that effected my
simulation. Interesting, once again the headers did not change. They
still show the file not being updated after 1996, ending with change
86.

I brought this up with the models in the past.

Is there a reason that you don't want to take the time to document
your work?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759