Why warnings: "Input <xyz> never used???"

[Chris Carlen]

Hi:

I am building my first Verilog project with Xilinx WebPack 5.2i.

I have a module test_delay8 that instantiates a module Delay8Bit, which
in turn instantiates two further modules, an 8-bit comparator and an
8-bit counter, where the counter is inferred from the XST library.

But I get lots of warnings about inputs and signals not used:

--------------------------------------------------------------------
Synthesizing Unit &lt;CB8CE&gt;.
Related source file is cb8ce.v.
Found 8-bit up counter for signal &lt;Q&gt;.
WARNING:Xst:647 - Input &lt;CE&gt; is never used.
Summary:
inferred 1 Counter(s).
Unit &lt;CB8CE&gt; synthesized.

Synthesizing Unit &lt;Delay8Bit&gt;.
Related source file is Delay8Bit.v.
WARNING:Xst:647 - Input &lt;Delay&lt;7&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;6&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;5&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;4&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;3&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;2&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;1&gt;&gt; is never used.
WARNING:Xst:647 - Input &lt;Delay&lt;0&gt;&gt; is never used.
Unit &lt;Delay8Bit&gt; synthesized.

Synthesizing Unit &lt;test_delay8&gt;.
Related source file is test_delay8.v.
WARNING:Xst:646 - Signal &lt;Delay_td&gt; is assigned but never used.
Unit &lt;test_delay8&gt; synthesized.
---------------------------------------------------------------------

The logic all seems to work, however.

What are these warnings all about? The signals certainly appear to be
used from my perspective. I would like to understand how to code so
that the warnings are not generated, since they are not confidence
inspiring.

Thanks for assistance

Good day!

P.S. Here are all the modules if you'd like to see. Feel free to
criticize my methods in addition to considering my original question:


module test_delay8(Trig_td, Out_td, Clk_td);
input wire Trig_td, Clk_td;
output wire Out_td;

wire [7:0] Delay_td;

assign Delay_td = 83;

Delay8Bit D1 (.Trig_in(Trig_td), .Out(Out_td), .Clk_in(Clk_td),

.Delay(Delay_td));

endmodule


module Delay8Bit(Trig_in, Out, Clk_in, Delay);
input wire Trig_in, Clk_in;
input wire [7:0] Delay;
output wire Out;

wire [7:0] Qc;
wire CompMatchOut;
wire nowhere1, nowhere2;
supply1 h;

CB8CE Counter1 ( .Q(Qc), .TC(nowhere1), .CE0(nowhere2),
.C(Clk_in), .CLR(~Out), .CE(h) );

Compare8 Comp1 (CompMatchOut, Qc, Delay);

FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );

endmodule


module Compare8(Q, A, B);
output wire Q;
input wire [7:0] A;
input wire [7:0] B;

wire X7, X6, X5, X4, X3, X2, X1, X0;

xnor
XNOR7 (X7, A[7], B[7]),
XNOR6 (X6, A[6], B[6]),
XNOR5 (X5, A[5], B[5]),
XNOR4 (X4, A[4], B[4]),
XNOR3 (X3, A[3], B[3]),
XNOR2 (X2, A[2], B[2]),
XNOR1 (X1, A[1], B[1]),
XNOR0 (X0, A[0], B[0]);

and (Q, X7, X6, X5, X4, X3, X2, X1, X0);

endmodule


module CB8CE(Q, TC, CE0, C, CLR, CE);
output reg [7:0] Q;
output reg TC, CE0;
input wire C, CLR, CE;

/* Here is the "Counter binary 8-bit async. clear with enable (CB8CE)"
inference code
from the Xilinx lib.pdf document: */
always @ (posedge C or posedge CLR)
begin
if (CLR)
Q &lt;= 0;
else if (CE)
Q &lt;= Q + 1;
end

always @ (Q)
begin
if (Q == 255)
TC &lt;= 1;
else
TC &lt;= 0;
end

always @ (CE or TC)
begin
CE0 &lt;= TC &amp;&amp; CE;
end
/* END of CB8CE inference code */

endmodule




--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Martin Euredjian]

Chris Carlen wrote:

I have a module test_delay8 that instantiates a module Delay8Bit, which
in turn instantiates two further modules, an 8-bit comparator and an
8-bit counter, where the counter is inferred from the XST library.

But I get lots of warnings about inputs and signals not used:

&lt;SNIP&gt;

WARNING:Xst:647 - Input &lt;Delay&lt;7&gt;&gt; is never used.

Chris,

I didn't have time to look at your code. I'll just offer a couple of
pointers here.

The Xilinx tools will optimize away logic you are not using. In doing so, a
path that you thought was complete might endup without logic to connect to.
A warning will be issued to let you know.

In general terms, take a look at your design and make sure that every single
signal contributes to physical chip outputs. That's the key. If a singnal,
say, the high bit of a counter, doesn't influence an output at all, the
tools will remove that flip-flop and anything else prior to that flip-flop
that does not add anything to the mix.

I soft of doesn't make sense in the context of building out a design, when
you might not have all the blocks ready. It can be a real pain. One
approach is to put in dummy blocks that do something with signals you are
not using yet (a large AND function, for example, with the single output
assigned to a pin).


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"

 

[Chris Carlen]

Martin Euredjian wrote:

Chris Carlen wrote:


I have a module test_delay8 that instantiates a module Delay8Bit, which
in turn instantiates two further modules, an 8-bit comparator and an
8-bit counter, where the counter is inferred from the XST library.

But I get lots of warnings about inputs and signals not used:


SNIP

WARNING:Xst:647 - Input &lt;Delay&lt;7&gt;&gt; is never used.


Chris,

I didn't have time to look at your code. I'll just offer a couple of
pointers here.

The Xilinx tools will optimize away logic you are not using. In doing so, a
path that you thought was complete might endup without logic to connect to.
A warning will be issued to let you know.

In general terms, take a look at your design and make sure that every single
signal contributes to physical chip outputs. That's the key. If a singnal,
say, the high bit of a counter, doesn't influence an output at all, the
tools will remove that flip-flop and anything else prior to that flip-flop
that does not add anything to the mix.

I soft of doesn't make sense in the context of building out a design, when
you might not have all the blocks ready. It can be a real pain. One
approach is to put in dummy blocks that do something with signals you are
not using yet (a large AND function, for example, with the single output
assigned to a pin).

Yeah, I gather what's happening is that it sees a constant applied to
the input of some function, and reduces the logic. In the process, the
input becomes superfluous.

Thanks for the reply.

Good day!


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Kevin Brace]

Hi Chris,

It's off topic, and it is probably none of my business to suggest (I
almost used the word "criticize," but I instead used "suggest," so that
you won't feel offended.), but why instantiate a vendor specific library
primitive and Verilog gate primitives when you don't have to?
These are the two examples I am talking about.
______________________________________________________________________
FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );

______________________________________________________________________


Why instantiate an FDC?
You should be able to replace it with the following code (Assuming that
what I am doing is correct), and the synthesis tool should infer you an
FDC.

______________________________________________________________________
reg Out;

always @ (posedge Trig_in or posedge CompMatchOut) begin

if (CompMatchOut == 1'b1) begin
Out &lt;= 1'b0;

end
else begin
Out &lt;= h;

end
end
______________________________________________________________________


______________________________________________________________________
module Compare8(Q, A, B);
output wire Q;
input wire [7:0] A;
input wire [7:0] B;

wire X7, X6, X5, X4, X3, X2, X1, X0;

xnor
XNOR7 (X7, A[7], B[7]),
XNOR6 (X6, A[6], B[6]),
XNOR5 (X5, A[5], B[5]),
XNOR4 (X4, A[4], B[4]),
XNOR3 (X3, A[3], B[3]),
XNOR2 (X2, A[2], B[2]),
XNOR1 (X1, A[1], B[1]),
XNOR0 (X0, A[0], B[0]);

and (Q, X7, X6, X5, X4, X3, X2, X1, X0);

endmodule
______________________________________________________________________


Also, why instantiate Verilog gate primitives when you should be
able to do the same thing for less code?
______________________________________________________________________
module Compare8(Q, A, B);
output Q;
input[7:0] A;
input[7:0] B;

assign Q = (A[7:0] == B[7:0]);

endmodule
______________________________________________________________________



I believe those two changes I made are correct, but you will
have to make sure that they work correctly.


Kevin Brace

 

[Chris Carlen]

Kevin Brace wrote:

Hi Chris,

It's off topic, and it is probably none of my business to suggest (I
almost used the word "criticize," but I instead used "suggest," so that
you won't feel offended.), but why instantiate a vendor specific library
primitive and Verilog gate primitives when you don't have to?
These are the two examples I am talking about.
______________________________________________________________________
FDC FF1 ( .Q(Out), .C(Trig_in), .CLR(CompMatchOut), .D(h) );

______________________________________________________________________


Why instantiate an FDC?
You should be able to replace it with the following code (Assuming that
what I am doing is correct), and the synthesis tool should infer you an
FDC.

______________________________________________________________________
reg Out;

always @ (posedge Trig_in or posedge CompMatchOut) begin

if (CompMatchOut == 1'b1) begin
Out &lt;= 1'b0;

end
else begin
Out &lt;= h;

end
end
______________________________________________________________________

Yes, of course. I appreciate your suggestions and if you want to
constructively criticize my posts in the future, that is welcome too. I
have noticed you are a very experienced poster here, so I will listen.

The only reason I am doing these silly things is twofold: 1. I am just
learning the language, and am on the chapters of "gate level modeling"
and "structural" modeling in my Verilog text.

So rather than do the boring exercises in the book, especially when I
have a real design that needs implementing, I decided to get comfortable
with structural modeling by implementing my first Verilog project in
mainly this way.

I also am trying to delve a little deeper into knowing how to work with
WebPack. I had only done schematics in the past, with a single source
module. This time I have multiple Verilog source modules. I have also
just begun learning about the libraries.

So it appears you are hinting that it is wiser to code generically
rather than invoke vendor libraries? I suppose this might make sense in
the broader sense, for portability, huh? Something I hadn't really
thought about until you prodded me.

So even if I were determined to model in the structural style, might you
suggest that I instead build the generic FDC using the code you have
shown, and which I can understand enough. Put it in a module called
FDC, then instantiate that?

______________________________________________________________________
module Compare8(Q, A, B);
output wire Q;
input wire [7:0] A;
input wire [7:0] B;

wire X7, X6, X5, X4, X3, X2, X1, X0;

xnor
XNOR7 (X7, A[7], B[7]),
XNOR6 (X6, A[6], B[6]),
XNOR5 (X5, A[5], B[5]),
XNOR4 (X4, A[4], B[4]),
XNOR3 (X3, A[3], B[3]),
XNOR2 (X2, A[2], B[2]),
XNOR1 (X1, A[1], B[1]),
XNOR0 (X0, A[0], B[0]);

and (Q, X7, X6, X5, X4, X3, X2, X1, X0);

endmodule
______________________________________________________________________

Also, why instantiate Verilog gate primitives when you should be
able to do the same thing for less code?

Well, it was kinda fun ;-) I am also learning digital logic design by
gradual experience, having never taking a formal course in it. So I
asked myself "how does one determine the equality of two binary words?"
I proceeded to twiddle with bits and bytes and truth tables on paper,
and came up with the above blob of gates. I proceeded to implement it
structurally, again just to cement my comfortability with this
inefficient coding style.

Then I discovered on further perusing the Xilinx library that they had
the same thing available to me already.

In the interest of learning I also experimented with the following way
in dataflow style:

assign Q = &amp; ( A ~^ B );

which seemed to work fine. I also wondered if it was possible to write
the operation in the way you show here:

______________________________________________________________________
module Compare8(Q, A, B);
output Q;
input[7:0] A;
input[7:0] B;

assign Q = (A[7:0] == B[7:0]);

endmodule
______________________________________________________________________

But actually, I wonder if you can do this:

assign Q = (A == B); // ???


Ok, thanks for the reply.

Good day!


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Kevin Brace]

Chris Carlen wrote:

Yes, of course. I appreciate your suggestions and if you want to
constructively criticize my posts in the future, that is welcome too. I
have noticed you are a very experienced poster here, so I will listen.

The only reason I am doing these silly things is twofold: 1. I am just
learning the language, and am on the chapters of "gate level modeling"
and "structural" modeling in my Verilog text.

Is the book you are using called Verilog Digital System Design by
Zainalabedin Navabi?
It sounds like that because that book gets into boring stuff like
structural modeling.

So rather than do the boring exercises in the book, especially when I
have a real design that needs implementing, I decided to get comfortable
with structural modeling by implementing my first Verilog project in
mainly this way.


So it appears you are hinting that it is wiser to code generically
rather than invoke vendor libraries? I suppose this might make sense in
the broader sense, for portability, huh? Something I hadn't really
thought about until you prodded me.

Right, you probably should avoid using vendor specific features
if there is no benefit like performance gain or logic resources
reduction.
Otherwise, keeping the logic generic makes sense for portability
reasons.

So even if I were determined to model in the structural style, might you
suggest that I instead build the generic FDC using the code you have
shown, and which I can understand enough. Put it in a module called
FDC, then instantiate that?

I am personally sure how to answer this question, but even if
you are interested in modeling a FF, in Verilog "reg" is as simple as
things get.
That being said, if you are interested in instantiating a vendor
specific primitive like FDC from Xilinx's primitive library (Other firms
have a similar primitive with similar names.), you can do that, but, of
course, the code will become vendor specific.

Well, it was kinda fun ;-) I am also learning digital logic design by
gradual experience, having never taking a formal course in it. So I
asked myself "how does one determine the equality of two binary words?"
I proceeded to twiddle with bits and bytes and truth tables on paper,
and came up with the above blob of gates. I proceeded to implement it
structurally, again just to cement my comfortability with this
inefficient coding style.

Because of synthesis tools, I haven't used truth tables for
years (Last time I did so in a college digital logic course.), however,
when I had to build timing critical logic, I ended up reverting back to
drawing gates on a paper (Really, equivalent of doing schematics.),
mapping those gates into 4-input LUTs (Look-Up Tables), convert the
paper schematics into Verilog assign statement equations using &amp; (AND),
| (OR), ^ (XOR), and ~ (NOT), and finally, slapping "keep" attribute of
a synthesis tool (XST in my case.) to the wires coming out of assign
statements to prevent the synthesis tool from messing up the carefully
crafted equations I wrote (Still, XST ignored the keep attribute in some
cases, but 95% of the equations survived intact.).
What I just described is a really low level coding style, and I wish I
didn't have to do so, but I had no choice.

Then I discovered on further perusing the Xilinx library that they had
the same thing available to me already.

In the interest of learning I also experimented with the following way
in dataflow style:

assign Q = &amp; ( A ~^ B );

which seemed to work fine. I also wondered if it was possible to write
the operation in the way you show here:


But actually, I wonder if you can do this:

assign Q = (A == B); // ???

Ok, thanks for the reply.

Good day!

Yes, the above "assign Q = (A == B);" should work, however, I
usually like to specify the bit range, so that nothing unexpected
happens.
Generally speaking, Verilog is not a strict language, and lets to do
things like comparison without specifying the bit range, however, I
heard (I am not 100% sure.) that VHDL may not let you do that.


Kevin Brace

 

[Chris Carlen]

Kevin Brace wrote:

Is the book you are using called Verilog Digital System Design by
Zainalabedin Navabi?
It sounds like that because that book gets into boring stuff like
structural modeling.

Bhasker, "A verilog HDL Primer." I also have the synthesis book, which
I'll read after the primer.

I figured I'd be safe doing some real-world projects using structural
modeling, since there isn't much to think about in terms of synthesis
issues at this level.

So there's another book that deals with boring structural modeling!

Right, you probably should avoid using vendor specific features
if there is no benefit like performance gain or logic resources
reduction.
Otherwise, keeping the logic generic makes sense for portability
reasons.

I see.



Thanks for the input.



Good day!

--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov