Why System Verilog

[Neil]

Can some one explain to me what is System Verilog and the advantages of
using it ?

Thanks
Niel

 

[Neil]

Thanks you

Niel

 

[Swapnajit Mittra]

Neil wrote:

Can some one explain to me what is System Verilog and the advantages
of
using it ?

Thanks
Niel

Lot of the noise that you are hearing are just that - they
are marketing noise. But once you get past that, there is not
much disagreement that this is perhaps the most concerted
effort to revamp Verilog (or, for that matter, any HDL)
that encompasses many important developments since the
last big revamp a decade ago i.e. 1364-1995. Three important
components of a design environment: testbench, assertion
and C interface along with basic syntax are brought under
the purview of a single language. Sure not everybody will
use everything, sure there are disagreements about the
implementation and nitty-gritty of syntaxes within the
working groups, but there are not much disagreement that
working under a single language helps you integrate the
components together without much hassle.

If you go to http://www.systemverilog.org, you will see a
lot of technical articles. Hope you will find that useful
to make a decision for yourself.

- Swapnajit.
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