Why syntax error when accessing bits of an array word?

[Gammaburst]

Why does Synplify emit a syntax error in this example?
My fault, or unsupported Verilog feature?
ModelSim and Xilinx XST don't complain.

module test (clk, din, dout);
input clk;
input [7:0] din;
output [7:0] dout;
reg [7:0] a[0:2];

always @(posedge clk) begin
a[0] <= din;
a[1] <= a[0]; // this line compiles fine
a[2] <= a[1][7:0]; // Synplify error: "expected ;"
end
assign dout = a[2];
endmodule

 

[Jim Wu]

; // Synplify error: "expected ;"

Bit slicing of a memory element is not supported in Verilog-1995, but it is
legal in Verilog-2001. Maybe Synplicity doesn't not support this yet.

Jim Wu
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

[Andy Peters]

Gammaburst <spambots@eat.this> wrote in message news:<06f1qv439uucjs93cdedlh4a43igh48tc2@4ax.com>...

Why does Synplify emit a syntax error in this example?
My fault, or unsupported Verilog feature?
ModelSim and Xilinx XST don't complain.

module test (clk, din, dout);
input clk;
input [7:0] din;
output [7:0] dout;
reg [7:0] a[0:2];

always @(posedge clk) begin
a[0] <= din;
a[1] <= a[0]; // this line compiles fine
a[2] <= a[1][7:0]; // Synplify error: "expected ;"
end
assign dout = a[2];
endmodule

This is a new feature added to Verilog-2001, which is supported in
recent versions of Synplify. Make sure the little checkbox selects
Verilog-2001!

=a

 

[Gammaburst]

On 30 Oct 2003 09:05:02 -0800, Bassman59a@yahoo.com (Andy Peters)
wrote:

Gammaburst <spambots@eat.this> wrote in message news:<06f1qv439uucjs93cdedlh4a43igh48tc2@4ax.com>...
Why does Synplify emit a syntax error in this example?
My fault, or unsupported Verilog feature?
ModelSim and Xilinx XST don't complain.

module test (clk, din, dout);
input clk;
input [7:0] din;
output [7:0] dout;
reg [7:0] a[0:2];

always @(posedge clk) begin
a[0] <= din;
a[1] <= a[0]; // this line compiles fine
a[2] <= a[1][7:0]; // Synplify error: "expected ;"
end
assign dout = a[2];
endmodule

This is a new feature added to Verilog-2001, which is supported in
recent versions of Synplify. Make sure the little checkbox selects
Verilog-2001!

It's version 7.3.3, and that option is enabled. Hmmm!