Why not use boolean all the time for synthesis?

Guest
Dear VHDL users,

A few days ago somebody asked on this list why not use bit instead of
std_logic. Actually why don't we use boolean instead of std_logic? (I am
interested in fpga synthesis.)
The main advantage is cleaner shorter code.
Instead of writing in a synchronous process:

if v < 10 and w > 20 then
a <= '1';
else
a <= '0';
end if;

then we have the shorter:

a <= v < 10 and w > 20;

and then rather than

if a = '1' then

we have

if a then

Better! I have been using for years std_logic everywhere, but the more I
think about it, the less reasons I see for it. What's your opinions?


Seb.
 
me@me.net wrote:

Dear VHDL users,

A few days ago somebody asked on this list why not use bit instead of
std_logic. Actually why don't we use boolean instead of std_logic?
Click to expand...
For a top entity port, boolean might be
a poor choice, but otherwise I agree.
Below the top level, go for clean code.
Sometimes a few boolean process variables
make a cleaner looking controller than
the conventional enum types.

-- Mike Treseler
 
Dear Seb,
dear Seb, believe me, I can't understand you, you wrote:
--if v < 10 and w > 20 then
-- a <= '1';
-- else
-- a <= '0';
-- end if;
--
--then we have the shorter:
--
-- a <= v < 10 and w > 20;

It's O'K for this revision, "a" will accept '1' or '0', however I can't
understend this assignment a <= v < 10 and w > 20; My question and the
question of your compiler is going to be: Warrning: What is the value of
the variable 'a'? If you can tell me, I'll accept your answer it won't be
problem, but I suppose that you forgot to write somethink. If I am wrong,
sorry. About your question, "Actually why don't we use boolean instead of
std_logic?" i can give you short answer, or will try to give you clean
explanation.
O'K boolean type have just two positions TRUE or FALSE. If you use these
logic levels, you can't represent signals, variables e.g. This type is
used just for logical revisions that produce TRUE or FALSE, YES or NO,
logic '1' or '0'. This isn't real value. For this reason, you should use
std_logic or std_logic_vector
I will be enjoy if you understand my explanation.
Best regards
Ivaylo Krumov
 
me@me.net wrote:
Dear VHDL users,

A few days ago somebody asked on this list why not use bit instead of
std_logic. Actually why don't we use boolean instead of std_logic? (I am
interested in fpga synthesis.)
The main advantage is cleaner shorter code.
Instead of writing in a synchronous process:

if v < 10 and w > 20 then
a <= '1';
else
a <= '0';
end if;

then we have the shorter:

a <= v < 10 and w > 20;

and then rather than

if a = '1' then

we have

if a then

Better! I have been using for years std_logic everywhere, but the more I
think about it, the less reasons I see for it. What's your opinions?
Click to expand...
I don't know if a boolean signal or variable is sythesizable or not.
But the reason that std_logic is used has been described here already.
The other states (other than 1/0 or true/false) allow for a simulation
to show uninitialized signals, unknown values due to signal conflicts
and invalid states due to timing errors on FFs and memory, not to
mention tri-state hi-Z values.

Has anyone tried synthesizing a boolean signal? Will that work? I
would expect it will synthesize.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Mike Treseler wrote:

For a top entity port, boolean might be
a poor choice, but otherwise I agree.
Below the top level, go for clean code.
Sometimes a few boolean process variables
make a cleaner looking controller than
the conventional enum types.

-- Mike Treseler
Thanks for your answer Mike, you're confirming my thoughts.
Click to expand...


Seb.
 
ivailokroumov wrote:
It's O'K for this revision, "a" will accept '1' or '0', however I can't
understend this assignment a <= v < 10 and w > 20; My question and the
question of your compiler is going to be: Warrning: What is the value of
the variable 'a'? If you can tell me, I'll accept your answer it won't be
problem, but I suppose that you forgot to write somethink.
No I haven't.
Click to expand...
v < 10 returns a boolean
w > 20 returns a boolean
the expression "v < 10 and w > 20" returns a boolean which is assigned
to the boolean signal a.

O'K boolean type have just two positions TRUE or FALSE. If you use these
logic levels, you can't represent signals, variables e.g. This type is
used just for logical revisions that produce TRUE or FALSE, YES or NO,
logic '1' or '0'. This isn't real value. For this reason, you should use
std_logic or std_logic_vector
Tristate aside, only the vales '0' and '1' of std_logic are used for
Click to expand...
synthesis. Therefore using boolean is equivalent in term of the logic
generated and as the advantage of cleaner code.

Seb.
 
rickman wrote:
I don't know if a boolean signal or variable is sythesizable or not.
Yes they are.
Click to expand...

But the reason that std_logic is used has been described here already.
The other states (other than 1/0 or true/false) allow for a simulation
to show uninitialized signals, unknown values due to signal conflicts
and invalid states due to timing errors on FFs and memory, not to
mention tri-state hi-Z values.
Z value is used for synthesis, but it is rare, mainly for top level
Click to expand...
trisate where it is not a good idea to use booleans anyway. The other
values are not used.

As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..

Seb.
 
me@me.net wrote:
rickman wrote:
I don't know if a boolean signal or variable is sythesizable or not.
Yes they are.

But the reason that std_logic is used has been described here already.
The other states (other than 1/0 or true/false) allow for a simulation
to show uninitialized signals, unknown values due to signal conflicts
and invalid states due to timing errors on FFs and memory, not to
mention tri-state hi-Z values.
Z value is used for synthesis, but it is rare, mainly for top level
trisate where it is not a good idea to use booleans anyway. The other
values are not used.

As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..
Click to expand...
That is *exactly* the problem. 'a' should not be defined if the data it
depends on is uninitialized. It is not clear what will happen in your
examples because I don't know what data type v and w are. While
thinking about this, I realize that I don't know what the default value
of an integer is. I am used to thinking in terms of "undefined", but I
am not sure VHDL support "undefined" unless the data type does.

Personally, I have no problems using std_logic. I don't see the
advantage of using boolean. I guess I have not given it much thought,
but I expect it would be harder to work with boolean when doing
arithmetic, counters, comparisons and other operations that normally use
integers. Standard functions are available that convert slv to and from
integer (via signed and unsigned). You would need to write your own to
use boolean.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman wrote:

As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..
Click to expand...
That would be 'u' for std_logic, and false for boolean.
This is a very small disadvange for simulation
of an internal node. No worse than using a
type enumeration or integer.

but I expect it would be harder to work with boolean when doing
arithmetic, counters, comparisons and other operations that normally use
integers.
Click to expand...
I don't think this is what the OP was advocating.
The example was a two-way conditional assignment.

-- Mike Treseler
 
rickman wrote:
me@me.net wrote:

As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..


That is *exactly* the problem. 'a' should not be defined if the data it
depends on is uninitialized. It is not clear what will happen in your
examples because I don't know what data type v and w are. While
thinking about this, I realize that I don't know what the default value
of an integer is. I am used to thinking in terms of "undefined", but I
am not sure VHDL support "undefined" unless the data type does.
In my examples I was thinking of v and w of type signed or unsigned. If
Click to expand...
for any reasons, one or the other were not initialized, then in both
cases a would not be undefined!! I mean you do not loose anything in
that example in using boolean instead of std_logic!!! You only gain
shorter code!!


Personally, I have no problems using std_logic. I don't see the
advantage of using boolean.
There is no problem using std_logic. But if you replace most of your
Click to expand...
std_logic by boolean (not for ports of of top level design) you are
likely to get nice shorter code, that's the point. Why use std_logic for
synthesis were it buys you very litte except longer code?


I guess I have not given it much thought,
but I expect it would be harder to work with boolean when doing
arithmetic, counters, comparisons and other operations that normally use
integers. Standard functions are available that convert slv to and from
integer (via signed and unsigned). You would need to write your own to
use boolean.
No change for buses, signed and unsigned and std_logic_vector.
Click to expand...


Seb.
 
As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..

Seb.
Click to expand...
Hi Seb,

Value of unintialized signals/varibles depends upon the type of the
signal/varaible. (precisly it is the left most value of the type ).
For std_logic it is '-' and 'false' for boolean.

Regards,
Mohammed khader.
 
me@me.net wrote:
Personally, I have no problems using std_logic. I don't see the
advantage of using boolean.
There is no problem using std_logic. But if you replace most of your
std_logic by boolean (not for ports of of top level design) you are
likely to get nice shorter code, that's the point. Why use std_logic for
synthesis were it buys you very litte except longer code?
Click to expand...
Your examples are very simple and short. In general, I would not find
the small advantage (if any in my opinion) of the way you wrote your
code to be worth using yet another signal type throughout your code. I
have used the boolean type when it was strictly for a flag. But most of
the time I don't know what changes will be made to the code and which
signals will be used how. So if I make a lot of my signals boolean, I
will likely want to change them back to std_logic when I find them to be
clumsy.

In your example, you use the boolean in an if statement. If I want to
use that boolean in an assignment, I either have to use an IF, a case, a
WHEN ELSE or a WITH SELECT, depending on the part of the code. I don't
know of any type conversions for boolean unless you write your own. Not
that this is hard, but you need to consider that as well.

I see what you are saying. The boolean type is useful and can be
synthesized. I personally don't see a large advantage to using it since
I prefer to keep most of my signals similar to avoid type conversions.
But I use integer in spite of that limitation. And I have used
boolean. I just would not use it widely, just as I don't use integer
widely, only for specific cases.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
"Mohammed A.khader" wrote:
As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..

Seb.

Hi Seb,

Value of unintialized signals/varibles depends upon the type of the
signal/varaible. (precisly it is the left most value of the type ).
For std_logic it is '-' and 'false' for boolean.
Click to expand...
Yes, I remember now, that is the rule. But I think the leftmost value
of std_logic is 'U'.

He is not advocating that boolean replace std_logic. He is simply
saying that there are cases where it will result in cleaner code. The
initialization problem is not that a boolean will or won't have an
initial value, it is that you can't see that sequential logic is
uninitialized when looking at boolean signals. This is similar to the
reason that std_logic is used in place of type bit. Bit has no
uninitialized value. If you use bit or boolean you will not see that
one of the inputs to the signal are undefined or otherwise not a valid
logic state.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
if v < 10 and w > 20 then
a <= '1';
else
a <= '0';
end if;

then we have the shorter:

a <= v < 10 and w > 20;
Click to expand...

Hi Seb,

I totally agree with you for the above code. But what when I want to
write following code.

if v < 10 and w > 20 then
a <= e; --- if vlaue assigned is variable not costant.
else
a <= b and d ;
end if;

For the above code using type bit is necessary . Hence it is not
possible to use boolean always for short cuts .

Regards,
Mohammed khader.
 
<me@me.net> escribió en el mensaje
news:4149ece6$0$17696$626a14ce@news.free.fr...
rickman wrote:
I don't know if a boolean signal or variable is sythesizable or not.
Yes they are.

But the reason that std_logic is used has been described here already.
The other states (other than 1/0 or true/false) allow for a simulation
to show uninitialized signals, unknown values due to signal conflicts
and invalid states due to timing errors on FFs and memory, not to
mention tri-state hi-Z values.
Z value is used for synthesis, but it is rare, mainly for top level
trisate where it is not a good idea to use booleans anyway. The other
values are not used.

As for unintialized signals, then notice that in the example I have
given, if v or w were uninitialized, then in both cases, a will have the
value of '0' for std_logic, and false for boolean..
Click to expand...
exactly, so how would you debug it? you have no way to know that it's value
it's false because it's uninitialized or because "v < 10 and w > 20" is not
met, of course it's easy to check when it's a small example, but it can be
timeconsuming if you're simulating a system that takes 4 days to simulate...
 
Seb and all,
I think using std_logic for logic values is the
right answer. To solve your immediate problem,
you can do this with std_logic with the following:

A <= '1' when v < 10 and w > 20 else '0' ;

While this is more complicated than what you want,
it does avoid the issue of not having 'X' or 'Z'
with boolean.

There is a proposal in the next language revision
that addresses issues with conditional contexts
and allows you the rewrite the following:
if A = '1' and B = '1' then

as:
if A and B then

For details of the proposal, see:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft18_boolean_equivalence.txt

This proposal is part of the VHDL-200X fast track
effort. VHDL-200X is organized under IEEE-SA.
While IEEE/IEEE-SA provides some infrastructure, they
do not provide any funding. Most of the work is
done by volunteers.

There are many levels of participation that are needed:
1) If you see something that you like that is
being done, let other people know.
In particular, let your EDA vendors know about
features that are critical to you. Support of EDA
standards by an EDA vendor is a business decision -
if implementing a standard (or the features of a new
revision of a standard) will bring value to them, then
they will support it.

2) If you know of an organization that can provide
funding for the LRM editing, please let me know.
One source certainly is the EDA vendors who benefit
from the standard, however, they are not good for
all of the funding.

3) Join the reflectors and participate in the standards work.
Not all of the work is detailed LRM work. For example,
we are getting ready to review some of the new package
proposals/implementations - this is a tedious task, but
certainly does not require deep LRM knowledge to accomplish.

Best Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Dear VHDL users,

A few days ago somebody asked on this list why not use bit instead of
std_logic. Actually why don't we use boolean instead of std_logic? (I am
interested in fpga synthesis.)
The main advantage is cleaner shorter code.
Instead of writing in a synchronous process:

if v < 10 and w > 20 then
a <= '1';
else
a <= '0';
end if;

then we have the shorter:

a <= v < 10 and w > 20;

and then rather than

if a = '1' then

we have

if a then

Better! I have been using for years std_logic everywhere, but the more I
think about it, the less reasons I see for it. What's your opinions?


Seb.
Click to expand...
 
One reason to use std_logic is for conflict resolution. For example,
consider the following:

signal a: boolean;

proc1: process(clk)
begin
a <= true;
end process;

....

proc2: process(clk)
begin
a <= false;
end process;

Now granted, this is incorrect code, but a _simulator_ is going to
accept it. If signal a were a std_logic, this assignment would result
in the signal being set to 'X', which is obvious in waveforms, while
with a boolean it would probably be set to FALSE. A synthesis tool is
going to catch the assignment, but in all likelyhood you're simulating
parts of the design before synthesizing it (aren't you?), and you're
going to be spending time trying to figure out why conditions aren't
being fulfilled when you expect them to be.

Also, if you have conditions based on the state of a signal in a bus,
say maybe a type field from a cell in a FIFO, it's probably easier to
just breakout the std_logic from the std_logic_vector instead of
performing the conversion.
 
O'k VHDL folks, I see that here we will post different opinions and
different view points. However, The main question is:
Is it correct or actually, is it better to be used boolean type than
std_logic?
What is our a goal, to write VHDL syntezable code which is correct logical
and to make real downloadable code or to make shorter and cleaner code? I
guess that is better to have real code.
Dear Mohamed, you wrote:
"I totally agree with you for the above code. But what when I want to
write following code.

if v < 10 and w > 20 then
a <= e; --- if vlaue assigned is variable not costant.
else
a <= b and d ;
end if;"
If you are going to use this code as look as is to be able to expect than
"if v < 10 and w > 20" then "a" will accept "e" if they are same type.
However "if v < 10 and w > 20" then " return FALSE then "a" will accept "b
and d", if all of them are same type.It does mean:
"The variable "a" assign the result which is actually The variable "d"
masked with The variable "b". Operator and is boolean operator and must be
used with booleand types. However The type std_logic (std_logic_vector)
contains within itself the range of The type boolean, therefore won't
produce ERROR.
 
Greg Balczarek wrote:
One reason to use std_logic is for conflict resolution. For example,
consider the following:

signal a: boolean;

proc1: process(clk)
begin
a <= true;
end process;

...

proc2: process(clk)
begin
a <= false;
end process;

Now granted, this is incorrect code, but a _simulator_ is going to
accept it. If signal a were a std_logic, this assignment would result
in the signal being set to 'X', which is obvious in waveforms, while
with a boolean it would probably be set to FALSE.
Definitely not!!! This code will throw an error at the compilation
Click to expand...
stage! Something along the lines of "multiple drivers for an unresolved
signal".

Seb.
 
Jim Lewis wrote:

Seb and all,
I think using std_logic for logic values is the
right answer. To solve your immediate problem,
you can do this with std_logic with the following:

A <= '1' when v < 10 and w > 20 else '0' ;
If you read my original post it says "in a synchronous process"...
Click to expand...

But the reference to the VHDL-200X boolean equivalence is interesting.

Seb.
 
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