Why no synthesis?

[Vazquez]

Dear Sir or Madame,

I have the following VHDL code for the description of
a RAM structure with some logic built around.

Why does QuartusII not synthesize it as a RAM structure using
the memory bits of Cyclone?

Thank you for your help.

Kind regards

Andrés Vázquez
G&D System Development


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE test_ram_package IS

CONSTANT ram_width : INTEGER := 8;
CONSTANT ram_depth : INTEGER := 2048;

TYPE ram IS ARRAY(0 to ram_depth - 1) of
std_logic_vector(ram_width-1 downto 0);
SUBTYPE address_vector IS INTEGER RANGE 0 to ram_depth - 1;

CONSTANT xram_width : INTEGER := 11;
CONSTANT xram_depth : INTEGER := 16;

TYPE xram IS ARRAY(0 to xram_depth - 1) of
std_logic_vector(xram_width-1 downto 0);
SUBTYPE xaddress_vector IS INTEGER RANGE 0 to xram_depth - 1;

END test_ram_package;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.test_ram_package.ALL;


ENTITY test_inferred_ram IS
PORT
( reset : IN std_logic;
clock1 : IN std_logic;
clock2 : IN std_logic;
data : IN std_logic_vector(7 downto 0);
write_address: IN address_vector;
read_address: IN xaddress_vector;
write_xaddress : IN xaddress_vector;
xdata : IN std_logic_vector(10 downto 0);
we : IN std_logic;
q : OUT std_logic_vector(7 downto 0)
);
END test_inferred_ram;

ARCHITECTURE rtl OF test_inferred_ram IS


SIGNAL ram_block : RAM;
SIGNAL xram_block : XRAM;
SIGNAL read_address_reg : xaddress_vector;
SIGNAL writing : std_logic;

BEGIN

PROCESS(clock1, reset)
BEGIN
IF reset='1' then
writing <='0';
ELSIF clock1'event and clock1='1' then
writing <= writing;
IF we = '1' and writing='0' THEN
writing <= '1';
ELSIF we='1' and writing='1' THEN
writing <= '0';
END IF;
END IF;
END PROCESS;

PROCESS (clock1)
BEGIN
IF clock1='1' and clock1'event then
ram_block <= ram_block;
xram_block <= xram_block;

IF we = '1' and writing='0' THEN
ram_block(write_address) <= data;
xram_block(write_xaddress) <= xdata;

ELSIF we='1' and writing='1' then
ram_block(write_address) <= data;
xram_block(write_xaddress) <= xdata;

END IF;

END IF;
END PROCESS;
END rtl;

 

[Mike Treseler]

Vazquez wrote:

Why does QuartusII not synthesize it as a RAM structure using
the memory bits of Cyclone?

see pg. 50
http://www.altera.com/literature/an/an238.pdf

-- Mike Treseler

 

[Vazquez]

Dear Mr Treseler,

thank youu for your answer. I have looked at the pdf-file you recommended.
On page 50 there is the VHDL description of a single-clock synchronous RAM,
but I use two clocks.
The problem seems to be the signal writing:
When I do not use it, the compiler inferres RAM-memory.
But it should not be such a big problem to combine the write-signal with a
writing signal! But the compiler seems to have a recognition problem of
the RAM structure when doing so.
I am trying to find out why, but without any success yet.

Thanks.

Kind regards

Andres Vazquez
G&D System Development


Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F85DCD8.60208@flukenetworks.com>...

Vazquez wrote:

Why does QuartusII not synthesize it as a RAM structure using
the memory bits of Cyclone?

see pg. 50
http://www.altera.com/literature/an/an238.pdf

-- Mike Treseler

 

[Mike Treseler]

Vazquez wrote:

Dear Mr Treseler,

thank youu for your answer. I have looked at the pdf-file you recommended.
On page 50 there is the VHDL description of a single-clock synchronous RAM,
but I use two clocks.

If you want to infer a dual clock ram,
you need to have a process for each clock.
See the architecture for lpm_ram_dp in

http://www.edif.org/lpmweb/more/220model.vhd

for an example.

However, if you want to simplify your timing
analysis, consider synchronizing your accesses
to a single clock and using a single clock ram.

-- Mike Treseler