Why MyHDL?

[Jan Decaluwe]

Hello:

MyHDL is a Python package for using Python as a
Hardware Description Language.

A new release is upcoming, and on this occasion
we have prepared a page about why MyHDL may
be useful to you:

http://www.myhdl.org/doku.php/why

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a hardware description language:
http://www.myhdl.org

 

[Mike Treseler]

Jan Decaluwe wrote:

A new release is upcoming, and on this occasion
we have prepared a page about why MyHDL may
be useful to you:
http://www.myhdl.org/doku.php/why

Thanks for the update.
You have been busy!
I agree with the points listed in the link.
For a hardware designer, new to text description,
this is a reasonable and economical path to logic design.

What has always intrigued me about MyHDL is the notion
of verifying clock algorithms using python.
I already do this using plain python
for quickly working out vector widths
and math algorithms for clocked synthesis code.

Of course, my python model is not synthesizable,
but VHDL and Python variables and functions port easily
and a manual conversion is not difficult.

To use MyHDL I would have to give up using variables
and revert to using the .next attribute instead.
While MyHDL is a huge improvement over the
first generation description languages
ABEL, AHDL, CUPL etc),
this is a step I may not be not ready for.

But this is a personal problem.
Most VHDL users don't use variables.

Good luck to you Jan.
When the testbench conversion is ready,
I will give it a try on one of my example designs.

-- Mike Treseler

 

[Jan Decaluwe]

Mike Treseler wrote:

To use MyHDL I would have to give up using variables

Most certainly not. On the contrary.

and revert to using the .next attribute instead.

..next is merely the MyHDL way for signal assignment.

While MyHDL is a huge improvement over the
first generation description languages
ABEL, AHDL, CUPL etc),
this is a step I may not be not ready for.

But this is a personal problem.
Most VHDL users don't use variables.

But they should. As should Verilog designers, and MyHDL
can help them to make that easier.

Mike, it's not like you suggest. Really not. I consider
myself the biggest variable fan (perhaps second to you).
I'm tired of ranting against those stupid rules that
forbid variables in synthesizable Verilog. Why would I
implement an HDL without support for variables?

Of course, with regard to conversion, there are restrictions
regarding the types that can be used. They are documented here:

http://www.myhdl.org/doc/0.6/manual/conversion.html#supported-types
http://www.myhdl.org/doc/0.6/manual/conversion.html#intbv-objects

I'm still proud of the following page, which (for once) compares
the use of signals with variables. Warning: to see the point,
you have to read it to the end.

http://www.myhdl.org/doku.php/cookbook:jc2

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
From Python to silicon:
http://www.myhdl.org

 

[Mike Treseler]

Jan Decaluwe wrote:

Mike Treseler wrote:

To use MyHDL I would have to give up using variables

Most certainly not. On the contrary.

I mean in the MyHDL *source*,
not the generated code.

Maybe I'm wrong.
I'll look thru the examples again.

-- Mike Treseler

 

[Jan Decaluwe]

Mike Treseler wrote:

Jan Decaluwe wrote:
Mike Treseler wrote:

To use MyHDL I would have to give up using variables

Most certainly not. On the contrary.

I mean in the MyHDL *source*,
not the generated code.

No, .next is only for signals. Other types of objects and
assignments are supported by the convertor, and (only) those
map to variables.

Now, neither Python nor MyHDL currently support your favorite
coding style of local interfaceless procedures. This is because
of Python's current scoping rules. Perhaps that explains some
of the confusion?

Below is a small example of how MyHDL currently supports
variables that keep state, as compared to a signal. The
generated VHDL code is added. Hopefully this will make
it clearer:

============================================================
from myhdl import *

def Example(clock, reset):

count_sig = Signal(intbv(0)[8:])

@instance
def logic():
count_var = intbv(0)[8:]
while True:
yield clock.posedge, reset.negedge
if reset == 0:
count_sig.next = 0
count_var[:] = 0
else:
assert count_sig == count_var # equal
count_sig.next = count_sig + 1
count_var += 1
assert count_sig == count_var - 1 # different!

return logic

=============================================================

The generated VHDL code:

========================================================

-- File: Example.vhd
-- Generated by MyHDL 0.6
-- Date: Mon Dec 22 11:12:11 2008

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_06.all;

entity Example is
port (
clock: in std_logic;
reset: in std_logic
);
end entity Example;

architecture MyHDL of Example is

signal count_sig: unsigned(7 downto 0);

begin


EXAMPLE_LOGIC: process (clock, reset) is
variable count_var: unsigned(7 downto 0);
begin
if (reset = '0') then
count_sig <= "00000000";
count_var := "00000000";
elsif rising_edge(clock) then
assert (count_sig = count_var)
report "*** AssertionError ***"
severity error;
count_sig <= (count_sig + 1);
count_var := (count_var + 1);
assert (count_sig = (count_var - 1))
report "*** AssertionError ***"
severity error;
end if;
end process EXAMPLE_LOGIC;

end architecture MyHDL;

=====================================================



--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a hardware description language:
http://www.myhdl.org