Why my timing parametrs don't show up in my verilog netlist

[harry]

Hi everybody,
I am trying to use Switch-RC in verilog XL to simulate a 20,000
transistor chip
for timing verification.
I am facing a number of problems.I follow the Verilog-Xl documention
from cadence
on switch-RC .I add timing parameters like tr,tf ,tz to my instances
in my schematics .But they don't show up in my verilog netlist ,Hence
I don't see any timing verification my my waveforms.
I have made all schematics in virtuoso composer using analog lib
parts,using nmos4 and pmos4.
I add timing parametrs to my instances from add properties menu on my
instances.
I then use verilog-XL to simulate it.But my timing parametrs don't
show up in my verilog netlist.
I am doing test on smaller circuits like standard cells of nand ,adder
,registers etc.

Any help would be highly appericiated.

Thanks to u all

Regards
Harry