Why my timing parametrs don't show up in my verilog netlist

[harry]

Hi everybody,
I am trying to use Switch-RC in verilog XL to simulate a 20,000
transistor chip
for timing verification.
I am facing a number of problems.I follow the Verilog-Xl documention
from cadence
on switch-RC .I add timing parameters like tr,tf ,tz to my instances
in my schematics .But they don't show up in my verilog netlist ,Hence
I don't see any timing verification my my waveforms.
I have made all schematics in virtuoso composer using analog lib
parts,using nmos4 and pmos4.
I add timing parametrs to my instances from add properties menu on my
instances.
I then use verilog-XL to simulate it.But my timing parametrs don't
show up in my verilog netlist.
I am doing test on smaller circuits like standard cells of nand ,adder
,registers etc.

Any help would be highly appericiated.

Thanks to u all

Regards
Harry

 

[Andrew Beckett]

I haven't used switch-RC for probably more than 10 years (since before I joined
Cadence), and in fact I think it's not really supported any more. I remember
when using it 10 years ago seeing some notice that it was end-of-lifed back then
(but perhaps my memory is fading).

However, I think that you probably need to enable the "Netlist Switch-RC" option
in the netlist options form on the Verilog-XL integration to get the timing
parameters.

As an equivalent, you can put:

simVerilogHandleSwitchRCData=t

in your .simrc file.

Regards,

Andrew.

On 5 Aug 2004 01:46:48 -0700, hsingh@ece.pdx.edu (harry) wrote:

Hi everybody,
I am trying to use Switch-RC in verilog XL to simulate a 20,000
transistor chip
for timing verification.
I am facing a number of problems.I follow the Verilog-Xl documention
from cadence
on switch-RC .I add timing parameters like tr,tf ,tz to my instances
in my schematics .But they don't show up in my verilog netlist ,Hence
I don't see any timing verification my my waveforms.
I have made all schematics in virtuoso composer using analog lib
parts,using nmos4 and pmos4.
I add timing parametrs to my instances from add properties menu on my
instances.
I then use verilog-XL to simulate it.But my timing parametrs don't
show up in my verilog netlist.
I am doing test on smaller circuits like standard cells of nand ,adder
,registers etc.

Any help would be highly appericiated.

Thanks to u all

Regards
Harry

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[harry]

Hi Andrew ,

thanks for ur feedback.I have selected netlist switch RC option in my
netlisting options.But I still don't see any timing parameters in my
verilog netlist.
I am using NCSU CDK design kit.I use version IC5.0.It still shiws me
netlist switch RC option ,in verilog XL netlisting Options.
If cadence has stopped supporting it.do u have any idea in which
version they stopped supporting it.
If it is not supported in my version of cadence,Do u know any other
switch-level simulator that is supported by cadence or atleast
compatible with cadence
(leaving IRSIM).
thanks again for ur help

Harry
hsingh@ece.pdx.edu

 

[harry]

Hi Andrew,
I was refering to verilog Xl documentation published in 2003.Its
netlisting options still show switch RC in it.Also openbook in my
version of cadence shows switch RC netlisting option in cadence.

harry
hsingh@ece.pdx.edu

Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<1cngh013j0onncos6lfdkusmgfm79486a3@4ax.com>...

I haven't used switch-RC for probably more than 10 years (since before I joined
Cadence), and in fact I think it's not really supported any more. I remember
when using it 10 years ago seeing some notice that it was end-of-lifed back then
(but perhaps my memory is fading).

However, I think that you probably need to enable the "Netlist Switch-RC" option
in the netlist options form on the Verilog-XL integration to get the timing
parameters.

As an equivalent, you can put:

simVerilogHandleSwitchRCData=t

in your .simrc file.

Regards,

Andrew.

On 5 Aug 2004 01:46:48 -0700, hsingh@ece.pdx.edu (harry) wrote:

Hi everybody,
I am trying to use Switch-RC in verilog XL to simulate a 20,000
transistor chip
for timing verification.
I am facing a number of problems.I follow the Verilog-Xl documention
from cadence
on switch-RC .I add timing parameters like tr,tf ,tz to my instances
in my schematics .But they don't show up in my verilog netlist ,Hence
I don't see any timing verification my my waveforms.
I have made all schematics in virtuoso composer using analog lib
parts,using nmos4 and pmos4.
I add timing parametrs to my instances from add properties menu on my
instances.
I then use verilog-XL to simulate it.But my timing parametrs don't
show up in my verilog netlist.
I am doing test on smaller circuits like standard cells of nand ,adder
,registers etc.

Any help would be highly appericiated.

Thanks to u all

Regards
Harry

 

[Andrew Beckett]

As I said, this is not really my area of expertise. I was just basing my answer
on memory, which may well be wrong...

Perhaps someone else can answer your questions?

Andrew.

On 13 Aug 2004 02:26:17 -0700, hsingh@ece.pdx.edu (harry) wrote:

Hi Andrew ,
thanks for ur feedback.I have selected netlist switch RC option in my
netlisting options.But I still don't see any timing parameters in my
verilog netlist.
I am using NCSU CDK design kit.I use version IC5.0.It still shiws me
netlist switch RC option ,in verilog XL netlisting Options.
If cadence has stopped supporting it.do u have any idea in which
version they stopped supporting it.
If it is not supported in my version of cadence,Do u know any other
switch-level simulator that is supported by cadence or atleast
compatible with cadence
(leaving IRSIM).
thanks again for ur help

Harry
hsingh@ece.pdx.edu

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd