why ISE par does not tell me all buffer usage?

[QiDaNei]

Hi,
I have a V2P7 design going through ISE 6.1, in checking out the PAR
report, it tells me in the device utilization section of this,

Number of BUFGMUXs 8 out of 16 50%

But go to timing report table,

+-------------------------+----------+------+------+------------+-------------+

| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max
Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+

|opb_bram_if_cntlr_1_port | | | |
| |
| _BRAM_Clk | BUFGMUX4S| No | 2300 | 0.626 |
1.763 |
+-------------------------+----------+------+------+------------+-------------+

| MHz33 | BUFGMUX5P| No | 560 | 0.168 |
1.310 |
+-------------------------+----------+------+------+------------+-------------+

| ddr_clk_90 | BUFGMUX2P| No | 166 | 0.059 |
1.307 |
+-------------------------+----------+------+------+------------+-------------+

| clk_90 | BUFGMUX1P| No | 12 | 0.048 |
1.298 |
+-------------------------+----------+------+------+------------+-------------+

| ppc_clk_s | BUFGMUX6S| No | 2 | 0.000 |
1.784 |
+-------------------------+----------+------+------+------------+-------------+

| JTGC405TCK | Local | | 1 | 0.000 |
2.514 |
+-------------------------+----------+------+------+------------+-------------+

you can see that only 5 BUFGMUX are report here. I wonder where are
the other 3 BUFGMUX consumed?
Could you give me some clue?

Thanks.

 

[Tungsten-W]

Try open it with FPGA Editor or Floorplanner and see where are all the clock
buffers.
I think timing report only reports the number of clocks you defined in the
UCF plus the clocks
derived from DCM...i am also new fpga user so i may not be correct...

Kelvin



QiDaNei <black@hotmail.com> wrote in message
news:403545C8.9252BD05@hotmail.com...

Hi,
I have a V2P7 design going through ISE 6.1, in checking out the PAR
report, it tells me in the device utilization section of this,

Number of BUFGMUXs 8 out of 16 50%

But go to timing report table,


+-------------------------+----------+------+------+------------+-----------

--+

| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max
Delay(ns)|

+-------------------------+----------+------+------+------------+-----------

--+

|opb_bram_if_cntlr_1_port | | | |
| |
| _BRAM_Clk | BUFGMUX4S| No | 2300 | 0.626 |
1.763 |

+-------------------------+----------+------+------+------------+-----------

--+

| MHz33 | BUFGMUX5P| No | 560 | 0.168 |
1.310 |

+-------------------------+----------+------+------+------------+-----------

--+

| ddr_clk_90 | BUFGMUX2P| No | 166 | 0.059 |
1.307 |

+-------------------------+----------+------+------+------------+-----------

--+

| clk_90 | BUFGMUX1P| No | 12 | 0.048 |
1.298 |

+-------------------------+----------+------+------+------------+-----------

--+

| ppc_clk_s | BUFGMUX6S| No | 2 | 0.000 |
1.784 |

+-------------------------+----------+------+------+------------+-----------

--+

| JTGC405TCK | Local | | 1 | 0.000 |
2.514 |

+-------------------------+----------+------+------+------------+-----------

--+

you can see that only 5 BUFGMUX are report here. I wonder where are
the other 3 BUFGMUX consumed?
Could you give me some clue?

Thanks.