Why is this not a locally static choice?

[Charles M. Elias]

In the following code fragment Active-HDL flagged the "case oe_l is" line as an
error because oe_l is not locally static. Why is this so? "numbuffs" is
not going to change during execution.

Best regards,

Charles

------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------
entity BiDir is
generic( bufflength : natural := 8;
numbuffs : natural := 4 );
port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
a : inout std_logic_vector( bufflength - 1 downto 0 );
b0 : inout std_logic_vector( bufflength - 1 downto 0 );
b1 : inout std_logic_vector( bufflength - 1 downto 0 );
b2 : inout std_logic_vector( bufflength - 1 downto 0 );
b3 : inout std_logic_vector( bufflength - 1 downto 0 );
dirab : in std_logic
);
end BiDir;
------------------------------------------------------------------------
architecture archBiDir of BiDir is

begin
pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
begin
case oe_l is
when "0111" =>
if dirab = '1' then
a <= ( others => 'Z' );
b0 <= a;
else
...

 

[Egbert Molenkamp]

Since you have used a generic for numbuffs you can instantiate multiple
entities of BiDir with different values for the generic. Therefore it is not
'locally' static.

If you change the line:
oe_l : in std_logic_vector( 0 to numbuffs - 1 );
in
oe_l : in std_logic_vector( 0 to 3 );
it will work.

Notice also that the line:
case oe_l is
when "0111" =>
Would give an error if the generic numbuffs is not equal to 4.

Egbert Molenkamp

"Charles M. Elias" <charles.elias@wpafb.af.mil> schreef in bericht
news:35849667.0306260321.e8ed0a5@posting.google.com...

In the following code fragment Active-HDL flagged the "case oe_l is" line
as an
error because oe_l is not locally static. Why is this so? "numbuffs" is
not going to change during execution.

Best regards,

Charles

------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------
entity BiDir is
generic( bufflength : natural := 8;
numbuffs : natural := 4 );
port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
a : inout std_logic_vector( bufflength - 1 downto 0 );
b0 : inout std_logic_vector( bufflength - 1 downto 0 );
b1 : inout std_logic_vector( bufflength - 1 downto 0 );
b2 : inout std_logic_vector( bufflength - 1 downto 0 );
b3 : inout std_logic_vector( bufflength - 1 downto 0 );
dirab : in std_logic
);
end BiDir;
------------------------------------------------------------------------
architecture archBiDir of BiDir is

begin
pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
begin
case oe_l is
when "0111" =
if dirab = '1' then
a <= ( others => 'Z' );
b0 <= a;
else
...

 

[Charles M. Elias]

"Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl> wrote in message news:<bder9n$pbt$1@ares.cs.utwente.nl>...

Since you have used a generic for numbuffs you can instantiate multiple
entities of BiDir with different values for the generic. Therefore it is not
'locally' static.

If you change the line:
oe_l : in std_logic_vector( 0 to numbuffs - 1 );
in
oe_l : in std_logic_vector( 0 to 3 );
it will work.

Notice also that the line:
case oe_l is
when "0111" =
Would give an error if the generic numbuffs is not equal to 4.

Egbert Molenkamp

"Charles M. Elias" <charles.elias@wpafb.af.mil> schreef in bericht
news:35849667.0306260321.e8ed0a5@posting.google.com...
In the following code fragment Active-HDL flagged the "case oe_l is" line
as an
error because oe_l is not locally static. Why is this so? "numbuffs" is
not going to change during execution.

Best regards,

Charles

------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------
entity BiDir is
generic( bufflength : natural := 8;
numbuffs : natural := 4 );
port ( oe_l : in std_logic_vector( 0 to numbuffs - 1 );
a : inout std_logic_vector( bufflength - 1 downto 0 );
b0 : inout std_logic_vector( bufflength - 1 downto 0 );
b1 : inout std_logic_vector( bufflength - 1 downto 0 );
b2 : inout std_logic_vector( bufflength - 1 downto 0 );
b3 : inout std_logic_vector( bufflength - 1 downto 0 );
dirab : in std_logic
);
end BiDir;
------------------------------------------------------------------------
architecture archBiDir of BiDir is

begin
pio : process( oe_l, dirab, a, b0, b1, b2, b3 )
begin
case oe_l is
when "0111" =
if dirab = '1' then
a <= ( others => 'Z' );
b0 <= a;
else
...

Egbert,

Thanks!

Charles