Why is the last value used to detect the rising edge

[fl]

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?








My question is a lot of process only uses the following to write clk
rising edge:


process (clk)
begin
if clk'event and clk='1'

end process;

I am confused with the above two usage.
Could you explain it for me? Thanks a lot.

 

On Sep 3, 8:43 pm, fl <rxjw...@gmail.com> wrote:

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?

My question is a lot of process only uses the following to write clk
rising edge:

process (clk)
begin
if clk'event and clk='1'

end process;

I am confused with the above two usage.
Could you explain it for me? Thanks a lot.

Redundant? It depends on what the type of the clk signal is. If it's a
std_logic, then the check for '0' is *not* redundant. A signal of
type std_logic can have nine different values ('X', '0', '1', 'L',
'H', 'Z', etc). The check for '0' will, in simulation at least, cause
the code inside the "if" statement only to run on a clean 0-to-1
transition. It would be ignored on, for example, an 'X' to '1'
transition. On the other hand, if the signal is of type "bit", which
only has values '0' and '1', then it *is* redundant.

In a more practical sense, though, synthesizers (as opposed to
simulators) will treat the second form (clk'event and clk='1') as a
shorthand for referring to the regular rising edge clock of a real
hardware flip-flop, and ignore any nuances about nine-level
enumerations. For synthesis, I'd think of the clk'last_value='0' term
as redundant, and possibly even confusing to a dumber synthesizer.

- Kenn

 

[Alan Fitch]

fl wrote:

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?








My question is a lot of process only uses the following to write clk
rising edge:


process (clk)
begin
if clk'event and clk='1'

end process;

I am confused with the above two usage.
Could you explain it for me? Thanks a lot.

Imagine you write a testbench with a clock generator

signal clk : std_logic;

begin

process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;

What happens at time 0? The initial value of clk is 'U', so at
time 0 ns + 1 delta clk changes from 'U' to '1'.

clk'event and clk = '1' will detect the transation from 'U' to '1' as a
clock edge.

clk'event and clk = '1' and clk'last_value ='0' will not

rising_edge(clk) will not

As the example you gave was a setup time measurement, it should only run
on a "real" clock edge, not a transition from 'U' to '1'.

As Peter says later in the thread, rising_edge(clk) is the easiest to use.

regards
Alan

P.S. Have a look at the code for rising_edge (in the source code for
std_logic_1164 in your simulator) and you'll see it uses 'last_value
inside the function!

--
Alan Fitch
Doulos
http://www.doulos.com

 

[Peter]

On 4 Sep, 02:43, fl <rxjw...@gmail.com> wrote:

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?

My question is a lot of process only uses the following to write clk
rising edge:

process (clk)
begin
if clk'event and clk='1'

end process;

I am confused with the above two usage.
Could you explain it for me? Thanks a lot.

Use rising_edge(clk) instead.

/Peter

 

[LittleAlex]

On Sep 3, 5:43 pm, fl <rxjw...@gmail.com> wrote:

I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?

No. The 1st clock will have clk'last_value='U'.

There is probably some initialization that needs to occur.

Alex

 

[Andy]

On Sep 3, 7:43 pm, fl <rxjw...@gmail.com> wrote:

I see the following in a VHDL book and some web tutorial.

Unfortunately there are a ton of books and tutorials that still use
archaic means of detecting the rising or falling edge of clocks. It
was only 15 years ago that standard functions rising_edge() and
falling_edge() were incorporated into the IEEE standard... These
functions correctly detect transitions to and from L and H also.

If, on the other hand, your example uses type bit/bit_vector, I don't
think these functions are defined for that data type, and the check
for last_value='0' is completely redundant.

Andy

 

[Jim Lewis]

fl wrote:

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is
it?

I think everyone got the redundancy, but they missed the humor.

I like to call this a "Valley Girl" check.
They want to be for-sure for-sure it is a rising edge.

By the way the code for ieee.std_logic_1164.rising_edge
has this plus a few extra things.

With a properly setup clock, there is no reason to
put this kind of check in your code. If you feel
really paranoid about clock, write a single assertion
to check it:

assert not is_x(Clk) report "clock is X" severity error ;

Personally I would not bother.

I saw this in code once that was written for the old
Mentor Autologic Synthesis tool. I also know that some synthesis
tools (good ones) at least at one point did not synthesize this
coding style (and perhaps still don't).

Note that even if a tool will synthesizes rising_edge, does not
guarantee that it will accept this code. Much of what is in the
standard packages is guided by tool directives (either in the form
of VHDL attributes or meta-comments).

Cheers,
Jim