P
Pasacco
Guest
Dear
I implemented 12-state controller and the operations are basically
ld 32bit data -> ld another 32bit data -> compare -> store into memory
The operation above is repeated 1024 times.....
Then I synthesized in FPGA tool.
Problem is that the area is too big (more than 10% of Vertex2pro),
though 'area' optimiation option was used.
When I do the same thing with 128 times of ld/ld/cmp/store, the area
was 3%.
I am wondering why this happens....
and I hope the area of FSM will be constant, regarless of the number of
ld/st...
If someone has this experience or idea, let me know....Thankyou
I implemented 12-state controller and the operations are basically
ld 32bit data -> ld another 32bit data -> compare -> store into memory
The operation above is repeated 1024 times.....
Then I synthesized in FPGA tool.
Problem is that the area is too big (more than 10% of Vertex2pro),
though 'area' optimiation option was used.
When I do the same thing with 128 times of ld/ld/cmp/store, the area
was 3%.
I am wondering why this happens....
and I hope the area of FSM will be constant, regarless of the number of
ld/st...
If someone has this experience or idea, let me know....Thankyou