Why doesn't this produce the logic I expect?

[Shannon]

This seems trivial. I'm clearly missing something very basic. Here
is the code:

process(reset, clk) is
begin
if(reset = '1') then
output <= FALSE;
elsif(rising_edge(clk)) then
if set = '0' then
output <= TRUE;
elsif trig <= '1' then
output <= FALSE;
end if;
end if;
end process;

What I expected this to produce was a type of priority mux feeding a
flip-flop. If set is '0' then output goes true (i.e highest
priority). If set is anything else then we check trig (i.e lower
priority). If trig is '1' then output goes false. Any other
conditions output should hold it's state.

The code produces the required flip-flop but completely ignores the
trig signal. The only signal feeding the input to the flip-flop is
set. I'm missing something fundamental here. Please help.

 

[Daniel Leu]

On Feb 10, 10:18 am, Shannon <sgo...@sbcglobal.net> wrote:

This seems trivial.  I'm clearly missing something very basic.  Here
is the code:

        process(reset, clk) is
        begin
                if(reset = '1') then
                        output <= FALSE;
                elsif(rising_edge(clk)) then
                        if set = '0' then
                                output <= TRUE;
                        elsif trig <= '1' then
                                output <= FALSE;
                        end if;
                end if;
        end process;

What I expected this to produce was a type of priority mux feeding a
flip-flop.  If set is '0' then output goes true (i.e highest
priority).  If set is anything else then we check trig (i.e lower
priority).  If trig is '1' then output goes false.  Any other
conditions output should hold it's state.

The code produces the required flip-flop but completely ignores the
trig signal.  The only signal feeding the input to the flip-flop is
set.  I'm missing something fundamental here.  Please help.

How about

                        elsif trig = '1' then
^^^^

Cheers,
Daniel

 

[Shannon]

On Feb 10, 10:41 am, Daniel Leu <daniel....@gmail.com> wrote:

On Feb 10, 10:18 am, Shannon <sgo...@sbcglobal.net> wrote:



This seems trivial.  I'm clearly missing something very basic.  Here
is the code:

        process(reset, clk) is
        begin
                if(reset = '1') then
                        output <= FALSE;
                elsif(rising_edge(clk)) then
                        if set = '0' then
                                output <= TRUE;
                        elsif trig <= '1' then
                                output <= FALSE;
                        end if;
                end if;
        end process;

What I expected this to produce was a type of priority mux feeding a
flip-flop.  If set is '0' then output goes true (i.e highest
priority).  If set is anything else then we check trig (i.e lower
priority).  If trig is '1' then output goes false.  Any other
conditions output should hold it's state.

The code produces the required flip-flop but completely ignores the
trig signal.  The only signal feeding the input to the flip-flop is
set.  I'm missing something fundamental here.  Please help.

How about

                        elsif trig = '1' then

                                    ^^^^

Cheers,
Daniel

It's just not fair! I just saw the typo about 30 seconds ago. Daniel
I guess I still owe you the +1 for finding it but I want it on the
internet's permanent record that I DID in fact see my typo BEFORE I
saw your reply. Is there a posting undo button? (going to hide under
a rock now)

 

[Andy]

It is a well known fact that posting unsolved problems on the internet
improves vision. ;^)

Andy