Why does the variable have error when compiling?

[Robert Willy]

Hi,

I build the following small project. Modelsim complains the error:

vlog -work work -vopt C:/modeltech_10.1c/examples/impinj/Page2_loop.v
Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sc_power3
** Error: C:/modeltech_10.1c/examples/impinj/Page2_loop.v(8): 'XPower'
already declared in this scope (sc_power3).


The code is exactly copied from a book.

Why does this it happen?


Thanks,




module sc_power3(
output [7:0] XPower,
output finished,
input [7:0] X,
input clk, start);

reg [7:0] ncount;
reg [7:0] XPower;

assign finished = (ncount == 0);

always@(posedge clk)
if (start) begin
XPower <= X;
ncount <= 2;
end
else if( !finished) begin
ncount <= ncount - 1;
XPower <= XPower * X;
end

endmodule

 

[Robert Willy]

On Friday, August 14, 2015 at 7:40:32 PM UTC-7, Richard Damon wrote:

On 8/14/15 8:07 PM, Robert Willy wrote:
Hi,

I build the following small project. Modelsim complains the error:

vlog -work work -vopt C:/modeltech_10.1c/examples/impinj/Page2_loop.v
Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sc_power3
** Error: C:/modeltech_10.1c/examples/impinj/Page2_loop.v(8): 'XPower'
already declared in this scope (sc_power3).


The code is exactly copied from a book.

Why does this it happen?


Thanks,




module sc_power3(
output [7:0] XPower,
output finished,
input [7:0] X,
input clk, start);

reg [7:0] ncount;
reg [7:0] XPower;

assign finished = (ncount == 0);

always@(posedge clk)
if (start) begin
XPower <= X;
ncount <= 2;
end
else if( !finished) begin
ncount <= ncount - 1;
XPower <= XPower * X;
end

endmodule


As the error says, XPower is declared as both an output and an reg, thus
later references won't know which to affect.

I supposed that some verilog version stuff have different grammar resulting this. If that is wrong, my FPGA book wrote verilog code in many examples.
So strange.

Thanks,

 

[Richard Damon]

On 8/14/15 8:07 PM, Robert Willy wrote:

Hi,

I build the following small project. Modelsim complains the error:

vlog -work work -vopt C:/modeltech_10.1c/examples/impinj/Page2_loop.v
Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sc_power3
** Error: C:/modeltech_10.1c/examples/impinj/Page2_loop.v(8): 'XPower'
already declared in this scope (sc_power3).


The code is exactly copied from a book.

Why does this it happen?


Thanks,




module sc_power3(
output [7:0] XPower,
output finished,
input [7:0] X,
input clk, start);

reg [7:0] ncount;
reg [7:0] XPower;

assign finished = (ncount == 0);

always@(posedge clk)
if (start) begin
XPower <= X;
ncount <= 2;
end
else if( !finished) begin
ncount <= ncount - 1;
XPower <= XPower * X;
end

endmodule

As the error says, XPower is declared as both an output and an reg, thus
later references won't know which to affect.

 

[Gabor]

On 8/14/2015 10:46 PM, Robert Willy wrote:

On Friday, August 14, 2015 at 7:40:32 PM UTC-7, Richard Damon wrote:
On 8/14/15 8:07 PM, Robert Willy wrote:
Hi,

I build the following small project. Modelsim complains the error:

vlog -work work -vopt C:/modeltech_10.1c/examples/impinj/Page2_loop.v
Model Technology ModelSim SE vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sc_power3
** Error: C:/modeltech_10.1c/examples/impinj/Page2_loop.v(8): 'XPower'
already declared in this scope (sc_power3).


The code is exactly copied from a book.

Why does this it happen?


Thanks,




module sc_power3(
output [7:0] XPower,
output finished,
input [7:0] X,
input clk, start);

reg [7:0] ncount;
reg [7:0] XPower;

assign finished = (ncount == 0);

always@(posedge clk)
if (start) begin
XPower <= X;
ncount <= 2;
end
else if( !finished) begin
ncount <= ncount - 1;
XPower <= XPower * X;
end

endmodule


As the error says, XPower is declared as both an output and an reg, thus
later references won't know which to affect.

I supposed that some verilog version stuff have different grammar resulting this. If that is wrong, my FPGA book wrote verilog code in many examples.
So strange.

Thanks,

In Verilog '95 you would normally have port names, followed by
declarations, including the signal type possibly on separate lines,
like:

module foo
(
a,
b,
c
);

input a;
output b;
output c;
reg c;

Then in Verilog 2001, you get the ability to place the declarations
right in the port list, and in this case you _must_ define the net
type in the declaration, not as an additional item.

So in the above case it would be:

module foo
(
input wire a, // or just input a if you use the default type of wire
output wire b, // again, could be just output b
output reg c
);

You can still use the older Verilog 95 syntax, and in that
case I believe it is all right to have output c and reg c
on separate lines, even using Verilog 2001.

--
Gabor