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David Rogoff
Guest
Sometimes the smart compile feature is great, but other times... I
have a Stratix chip in Quartus II v4sp1. All I did was go into
Assignment Editor and change a couple of pins from one I/O standard to
another. There were no changes to my RTL code. As expected, it umped
through synthesis in a minute. However, I expected the fitter to just
take a few minutes since there was no placement or routing changes.
Instead, it's taken 2 hours, and it's only at 51%. This is about as
long as a full place and route. Why is it doing this!?!?!?
David
have a Stratix chip in Quartus II v4sp1. All I did was go into
Assignment Editor and change a couple of pins from one I/O standard to
another. There were no changes to my RTL code. As expected, it umped
through synthesis in a minute. However, I expected the fitter to just
take a few minutes since there was no placement or routing changes.
Instead, it's taken 2 hours, and it's only at 51%. This is about as
long as a full place and route. Why is it doing this!?!?!?
David