Why does it use shared variable?

F

fl

Guest
Hi,
When I learn Modelsim, I find that there is shared variable in its single port
memory example. Every architecture of sp_syn_ram has its
SHARED VARIABLE mem : mem_type;

I do not see one mem variable accessed by other process signals.

I only copy two architectures below of the four similar structures.

Do you think what purpose it uses shared variable here?

Thanks,



..........................
ARCHITECTURE constrainedintarch OF sp_syn_ram IS

SUBTYPE constrained_int is integer range 0 to 2**data_width-1;
TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int;
SHARED VARIABLE mem : mem_type;

BEGIN

ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
mem(to_integer(addr)) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length));
END IF;
END PROCESS;

END constrainedintarch;


ARCHITECTURE \3D\ OF sp_syn_ram IS

TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer;
SHARED VARIABLE mem : mem_type;

BEGIN

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
IF (we = '1') THEN
mem(outer_addr, inner_addr) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length));
END IF;
END PROCESS;

END \3D\;
 
fl wrote:
Hi,
When I learn Modelsim, I find that there is shared variable in its single port
memory example. Every architecture of sp_syn_ram has its
SHARED VARIABLE mem : mem_type;

I do not see one mem variable accessed by other process signals.

I only copy two architectures below of the four similar structures.

Do you think what purpose it uses shared variable here?

Thanks,



.........................
ARCHITECTURE constrainedintarch OF sp_syn_ram IS

SUBTYPE constrained_int is integer range 0 to 2**data_width-1;
TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int;
SHARED VARIABLE mem : mem_type;

BEGIN

ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
mem(to_integer(addr)) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length));
END IF;
END PROCESS;

END constrainedintarch;


ARCHITECTURE \3D\ OF sp_syn_ram IS

TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer;
SHARED VARIABLE mem : mem_type;

BEGIN

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
IF (we = '1') THEN
mem(outer_addr, inner_addr) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length));
END IF;
END PROCESS;

END \3D\;
Click to expand...

Just a guess, perhaps the one-port memory example was chopped down from
a two-port memory example?

--
Gabor
 
On Thursday, June 26, 2014 10:34:24 AM UTC-5, HT-Lab wrote:
> There are 2 different clocks, one for reading and one for writing used in the same process. Run the simulation and check the result, next change the shared variable to a signal and see what happens, Good luck, Hans.

I think the OP was referring to changing the shared variable to a local variable declared in the process, not to a signal. A local variable would behave exactly the same as the shared variable in this context.

Using a shared variable, IINM, allows the memory content to be accessed with a hierarchical reference, say in a testbench, etc. Local variables do not allow that (yet).

Andy
 
On 26/06/2014 03:47, fl wrote:
Hi,
When I learn Modelsim, I find that there is shared variable in its single port
memory example. Every architecture of sp_syn_ram has its
SHARED VARIABLE mem : mem_type;

I do not see one mem variable accessed by other process signals.
Click to expand...

There are 2 different clocks, one for reading and one for writing used
in the same process. Run the simulation and check the result, next
change the shared variable to a signal and see what happens,

Good luck,
Hans.
www.ht-lab.com

I only copy two architectures below of the four similar structures.

Do you think what purpose it uses shared variable here?

Thanks,



.........................
ARCHITECTURE constrainedintarch OF sp_syn_ram IS

SUBTYPE constrained_int is integer range 0 to 2**data_width-1;
TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int;
SHARED VARIABLE mem : mem_type;

BEGIN

ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
mem(to_integer(addr)) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length));
END IF;
END PROCESS;

END constrainedintarch;


ARCHITECTURE \3D\ OF sp_syn_ram IS

TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer;
SHARED VARIABLE mem : mem_type;

BEGIN

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
IF (we = '1') THEN
mem(outer_addr, inner_addr) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length));
END IF;
END PROCESS;

END \3D\;
Click to expand...
 
HT-Lab wrote:
On 26/06/2014 03:47, fl wrote:
Hi,
When I learn Modelsim, I find that there is shared variable in its
single port
memory example. Every architecture of sp_syn_ram has its
SHARED VARIABLE mem : mem_type;

I do not see one mem variable accessed by other process signals.

There are 2 different clocks, one for reading and one for writing used
in the same process. Run the simulation and check the result, next
change the shared variable to a signal and see what happens,

Good luck,
Hans.
www.ht-lab.com


I only copy two architectures below of the four similar structures.

Do you think what purpose it uses shared variable here?

Thanks,



.........................
ARCHITECTURE constrainedintarch OF sp_syn_ram IS

SUBTYPE constrained_int is integer range 0 to 2**data_width-1;
TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int;
SHARED VARIABLE mem : mem_type;

BEGIN

ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
mem(to_integer(addr)) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
data_out <=
std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length));
END IF;
END PROCESS;

END constrainedintarch;


ARCHITECTURE \3D\ OF sp_syn_ram IS

TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF
integer;
SHARED VARIABLE mem : mem_type;

BEGIN

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO
addr_width-2));
IF (we = '1') THEN
mem(outer_addr, inner_addr) :=
to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO
addr_width-2));
data_out <= std_logic_vector(to_unsigned(mem(outer_addr,
inner_addr), data_out'length));
END IF;
END PROCESS;

END \3D\;
Click to expand...

I think the question was about sharing, rather than whether this should
be a signal. i.e. if it's only used in one process, why does the
variable "mem" need to be shared?

--
Gabor
 
Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP.

Kevin Jennings
 
On 27/06/2014 02:12, KJ wrote:
Unless the two clocks are actually the same clock, there should be no difference when using variables or signals in the posted code...but as noted by others signal vs variable did not appear to be the point of the OP.

Kevin Jennings
Click to expand...
you are all correct, I misread the OP's question. A shared variable in
this case is not required and a local process variable should behave the
same.

Regards,
Hans
www.ht-lab.com
 
Am 26.06.2014 04:47, schrieb fl:
Hi,
When I learn Modelsim, I find that there is shared variable in its single port
memory example. Every architecture of sp_syn_ram has its
SHARED VARIABLE mem : mem_type;

I do not see one mem variable accessed by other process signals.

I only copy two architectures below of the four similar structures.

Do you think what purpose it uses shared variable here?

Thanks,



.........................
ARCHITECTURE constrainedintarch OF sp_syn_ram IS

SUBTYPE constrained_int is integer range 0 to 2**data_width-1;
TYPE mem_type IS ARRAY (0 TO 2**addr_width-1) OF constrained_int;
SHARED VARIABLE mem : mem_type;

BEGIN

ASSERT data_width <= 32
REPORT "### Illegal data width detected"
SEVERITY failure;

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
IF (we = '1') THEN
mem(to_integer(addr)) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
data_out <= std_logic_vector(to_unsigned(mem(to_integer(addr)), data_out'length));
END IF;
END PROCESS;

END constrainedintarch;


ARCHITECTURE \3D\ OF sp_syn_ram IS

TYPE mem_type IS ARRAY (0 TO 3, 0 TO 2**(addr_width-2)-1) OF integer;
SHARED VARIABLE mem : mem_type;

BEGIN

control_proc : PROCESS (inclk, outclk)
VARIABLE inner_addr : integer;
VARIABLE outer_addr : integer;
BEGIN
IF (inclk'event AND inclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
IF (we = '1') THEN
mem(outer_addr, inner_addr) := to_integer(unsigned(data_in));
END IF;
END IF;

IF (outclk'event AND outclk = '1') THEN
inner_addr := to_integer(addr(addr_width-3 DOWNTO 0));
outer_addr := to_integer(addr(addr_width-1 DOWNTO addr_width-2));
data_out <= std_logic_vector(to_unsigned(mem(outer_addr, inner_addr), data_out'length));
END IF;
END PROCESS;

END \3D\;
Click to expand...

signals have attributes which the simulator must maintain.
(shared) variables do not. This makes simulation (much) faster.
Like signals, shared variables can be used for communication
between processes.

Regards, Markus
 
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