Guest
Hi,
Please see the following short piece of verilog code:
wire [63:0] xxx_bits = 64'h5;
real xxx_real;
reg [63:0] xxx_btbits;
integer xxx_int;
always @(posedge clk or xxx_bits ) begin
xxx_real = $bitstoreal(xxx_bits);
xxx_int = $rtoi(xxx_real);
xxx_btbits = $realtobits(xxx_real); //btbits=back to bits
end
The simulation results are:
xxx_bits = 0000000000000005
xxx_real = 2.47033e-323
xxx_int = 00000000
xxx_btbits = 0000000000000005
I would expect that the value of xxx_real should be "5". If xxx_real
were "5", then xxx_int would also be "5" and everything would make
sense. Am I missing something here?? Any help will be really
appreciated.
Please see the following short piece of verilog code:
wire [63:0] xxx_bits = 64'h5;
real xxx_real;
reg [63:0] xxx_btbits;
integer xxx_int;
always @(posedge clk or xxx_bits ) begin
xxx_real = $bitstoreal(xxx_bits);
xxx_int = $rtoi(xxx_real);
xxx_btbits = $realtobits(xxx_real); //btbits=back to bits
end
The simulation results are:
xxx_bits = 0000000000000005
xxx_real = 2.47033e-323
xxx_int = 00000000
xxx_btbits = 0000000000000005
I would expect that the value of xxx_real should be "5". If xxx_real
were "5", then xxx_int would also be "5" and everything would make
sense. Am I missing something here?? Any help will be really
appreciated.