Why are these signal inferred latches?

The Xilinx ISE 7.1i synthesis software gives warning messages that the
following signals are 1-bit latches: b_reg_strb, mod_pri_ready and
b_reg_ena. Below is the code for the state machine where these signals
are controlled. I don't see why they should be inferred as latches.
What am I missing?
----------------------------------------------------------------------------------------------------------------------------------
-- Slave Modify PRI Control State Machine Clocking and Initialization
----------------------------------------------------------------------------------------------------------------------------------
AddCtrlClking : process ( clk, clr, add_ctrl_next_state )

begin
if rising_edge( clk ) then
if clr = '1' then
add_ctrl_pres_state <= wait_load_cmd;
else
add_ctrl_pres_state <= add_ctrl_next_state;
end if;
end if;
end process AddCtrlClking;
-----------------------------------------------------------------------------------------------------------------------------------
-- Slave Modify PRI Control State Machine Output Control
-----------------------------------------------------------------------------------------------------------------------------------
AddCtrl : process( add_ctrl_pres_state, mod_pri_cmd, i_ld_mod_pri_wrd,

ena_buff, load_pri, add_sub_ena )
begin
case add_ctrl_pres_state is
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_load_cmd =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '1';
b_reg_ena <= '0';

if i_ld_mod_pri_wrd = '1' then
b_reg_strb <= '1';
add_ctrl_next_state <= wait_mod_pri_cmd;
else
b_reg_strb <= '0';
add_ctrl_next_state <= wait_load_cmd;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_mod_pri_cmd =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '1';
b_reg_ena <= '0';
b_reg_strb <= '0';

if mod_pri_cmd = '1' then
add_ctrl_next_state <= wait_buff_read;
else
add_ctrl_next_state <= wait_mod_pri_cmd;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_buff_read =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= ena_buff and add_sub_ena;
b_reg_strb <= '0';

if ena_buff = '1' then
add_ctrl_next_state <= mod_pri;
else
add_ctrl_next_state <= wait_buff_read;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when mod_pri =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= add_sub_ena;
b_reg_strb <= '0';

if load_pri = '1' then
add_ctrl_next_state <= wait_cmd_0;
else
add_ctrl_next_state <= mod_pri;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_cmd_0 =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= '0';
b_reg_strb <= '0';

if mod_pri_cmd = '0' then
add_ctrl_next_state <= wait_load_cmd;
else
add_ctrl_next_state <= wait_cmd_0;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when others =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
add_ctrl_next_state <= wait_load_cmd;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
end case;
end process AddCtrl;

 

Inferred latches are created because those 3 signals aren't set in
-every- path through AddCtrl process. ('when others' is one path I
saw.)

You can add defaults before the case statement.

Hope that helps,
G.

 

[David Binnie]

They are latches because these signals are dependent on a level not an edge.


<charles.elias@wpafb.af.mil> wrote in message
news:1135188759.688449.134050@g47g2000cwa.googlegroups.com...

The Xilinx ISE 7.1i synthesis software gives warning messages that the
following signals are 1-bit latches: b_reg_strb, mod_pri_ready and
b_reg_ena. Below is the code for the state machine where these signals
are controlled. I don't see why they should be inferred as latches.
What am I missing?
----------------------------------------------------------------------------------------------------------------------------------
-- Slave Modify PRI Control State Machine Clocking and Initialization
----------------------------------------------------------------------------------------------------------------------------------
AddCtrlClking : process ( clk, clr, add_ctrl_next_state )

begin
if rising_edge( clk ) then
if clr = '1' then
add_ctrl_pres_state <= wait_load_cmd;
else
add_ctrl_pres_state <= add_ctrl_next_state;
end if;
end if;
end process AddCtrlClking;
-----------------------------------------------------------------------------------------------------------------------------------
-- Slave Modify PRI Control State Machine Output Control
-----------------------------------------------------------------------------------------------------------------------------------
AddCtrl : process( add_ctrl_pres_state, mod_pri_cmd, i_ld_mod_pri_wrd,

ena_buff, load_pri, add_sub_ena )
begin
case add_ctrl_pres_state is
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_load_cmd =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '1';
b_reg_ena <= '0';

if i_ld_mod_pri_wrd = '1' then
b_reg_strb <= '1';
add_ctrl_next_state <= wait_mod_pri_cmd;
else
b_reg_strb <= '0';
add_ctrl_next_state <= wait_load_cmd;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_mod_pri_cmd =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '1';
b_reg_ena <= '0';
b_reg_strb <= '0';

if mod_pri_cmd = '1' then
add_ctrl_next_state <= wait_buff_read;
else
add_ctrl_next_state <= wait_mod_pri_cmd;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_buff_read =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= ena_buff and add_sub_ena;
b_reg_strb <= '0';

if ena_buff = '1' then
add_ctrl_next_state <= mod_pri;
else
add_ctrl_next_state <= wait_buff_read;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when mod_pri =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= add_sub_ena;
b_reg_strb <= '0';

if load_pri = '1' then
add_ctrl_next_state <= wait_cmd_0;
else
add_ctrl_next_state <= mod_pri;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when wait_cmd_0 =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
mod_pri_ready <= '0';
b_reg_ena <= '0';
b_reg_strb <= '0';

if mod_pri_cmd = '0' then
add_ctrl_next_state <= wait_load_cmd;
else
add_ctrl_next_state <= wait_cmd_0;
end if;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
when others =
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
add_ctrl_next_state <= wait_load_cmd;
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
end case;
end process AddCtrl;