Why 18X18 Multipliers in Altera and Xilinx?

[debo]

Most of the commercial DSP processors today have 16X16 or 32X32 bit
signed multilpiers. Why do Altera and Xilinx provide 18X18
multilpiers?

Also, what is the use of a single parity bit with each byte? As far as
i can understand it will only allow for error detection for a single
bit flip (which is the simplest form of error detection). Are there
any other uses of this parity bit?

 

[General Schvantzkoph]

On Mon, 05 Jul 2004 04:57:43 -0700, debo wrote:

Most of the commercial DSP processors today have 16X16 or 32X32 bit
signed multilpiers. Why do Altera and Xilinx provide 18X18
multilpiers?

Also, what is the use of a single parity bit with each byte? As far as
i can understand it will only allow for error detection for a single
bit flip (which is the simplest form of error detection). Are there
any other uses of this parity bit?

Single bit error detection is sufficient for most applications. If you are
using 64 bit data paths then 1 bit per byte adds up to eight extra bits
which is sufficient for a single bit correction, double bit detection ECC
code.

 

[Gabor Szakacs]

Actually 18 bits makes sense for parity, which is why the
block RAMs are 18 or 36 bits wide rather than 16 or 32. The
multiplier would normally only work on data, not parity. My
guess is that Xilinx picked 18 bits to use the common routing
resources available at the block RAM site (each multiplier
shares routing with an adjacent 18 Kbit block RAM). In an
FPGA data width is arbitrary unless you're using an embedded
processor. 18 bits is as reasonable a size as any other, and
2 bits better than 16 (you don't have to use all the bits).
Routing resource sharing shows up when you try to use the
block RAM at 36-bit width and realize the multiplier is no
longer usable.

General Schvantzkoph <schvantzkoph@yahoo.com> wrote in message news:<pan.2004.07.05.12.53.56.811963@yahoo.com>...

On Mon, 05 Jul 2004 04:57:43 -0700, debo wrote:

Most of the commercial DSP processors today have 16X16 or 32X32 bit
signed multilpiers. Why do Altera and Xilinx provide 18X18
multilpiers?

Also, what is the use of a single parity bit with each byte? As far as
i can understand it will only allow for error detection for a single
bit flip (which is the simplest form of error detection). Are there
any other uses of this parity bit?

Single bit error detection is sufficient for most applications. If you are
using 64 bit data paths then 1 bit per byte adds up to eight extra bits
which is sufficient for a single bit correction, double bit detection ECC
code.

 

Hello Gabor,

Your reply seems reasonable but that cannot explain why even Altera
gives 18X18 multilpiers?
You are right that in case of an FPGA any data width would do, but if
we look at the conventional DSP designs or DSP processors we see that
normally 8bits, 16bits or 32 bits are used. This would mean that many
of the designs that are imeplemented in these FPGAs would also have
8/16/32 bit data widths.
So does this mean that Xilinx gave it to integrate with its memory and
Altera gave it because XIlinx gave it?

Regards,
Deboleena.