Guest
Recently i used the xfuzzy software create vhdl code.
It was created vhdl code that used to xilinx edk add new project.
and i search some information or literatures.
It show GPIO and hardware BUS approaches.
So i want to use GPIO approach build xfuzzy ip.
my builded ways is :
1- add to xps_GPIO to system assembly view of edk and connect peripheral BUS
2- generate addresses to instance
3-modify the fuzzy ip port.
this part ,case is my edk proj have gpio system and i want to use in1ăin2ăout1ăpipeline port connect it .
But i am how to connect those port to gpio system.
because i modify mhs and add xfuzzy ip with top.vhd document together.
Moreover this is my first time design this project, it is let me feel orderless to work.
who can somebody give suggest or other method?
In here i post my original source code and project file.
https://mega.co.nz/#!KU43XTKa!oJiLRPmI0OYIAAHcGQVxLhBoF3QYLxWp4cXA0PUnsY0
It was created vhdl code that used to xilinx edk add new project.
and i search some information or literatures.
It show GPIO and hardware BUS approaches.
So i want to use GPIO approach build xfuzzy ip.
my builded ways is :
1- add to xps_GPIO to system assembly view of edk and connect peripheral BUS
2- generate addresses to instance
3-modify the fuzzy ip port.
this part ,case is my edk proj have gpio system and i want to use in1ăin2ăout1ăpipeline port connect it .
But i am how to connect those port to gpio system.
because i modify mhs and add xfuzzy ip with top.vhd document together.
Moreover this is my first time design this project, it is let me feel orderless to work.
who can somebody give suggest or other method?
In here i post my original source code and project file.
https://mega.co.nz/#!KU43XTKa!oJiLRPmI0OYIAAHcGQVxLhBoF3QYLxWp4cXA0PUnsY0