while loop

J

jiten

Guest
hi,
can anyone tell me while loop is synthesizable with synplify tool or
not?
plz help me out.
hoping a positive reply from all.
thanx.
jiten
 
hi all,
i've checked while loop without clock & with clock.
but its not getting synthesized with synplify-pro.
however,if i sunthesize with xilinx project manager it
synthesized
completely with all conditions.
Is there any problem with while loop in synplify pro.
plz help me out.
jiten
Mike Treseler wrote:
jiten wrote:

can anyone tell me while loop is synthesizable with synplify tool or
not?

Since a synthesis process loops all by
itself, every clock tick, I can't
imagine how you would use a while loop.
Let's see the code.

Sequential statements execute in zero time.
They form a testable logical description,
not a real-time program thread.

If you want a time delay, use a counter variable.

-- Mike Treseler
Click to expand...
 
I would be very cautious with ISE results since synplify does a very
good job. check out whether it has actually synthesized or just ignored
it.
 
its giving error that "while loop is not terminating", but i tried all
conditions such that it can be terminated easily. even i tried exit
condition also inside the while loop.
what is the problem...............................?
plz help.
thanx
 
Hey , in general a while loop is not synthesizable. do the same thing
with an if condition.
 
ya, it is working properly with "for" loop.
can any one suggest me how can i do it with while loop.
 
hi all,
in sinplfy pro , i m actually getting this error
"while loop is not terminating? you can set the maximum number of
loop
iterations with the syn_looplimit attribute."
what does it means?
 
It requires that the number of iterations be fixed, so it should be
deterministic.
 
hi the code is like this

process(cnt,tmp,rst)
begin
if rst='1' then
cnt <= "0000";
tmp <= "000";
i <= 0;
else
w : while i< 8 loop
tmp <= tmp+1;
cnt <= cnt+1;
i <= i + 1;
end loop w;
end if;
end process;
 
jiten wrote:
hi the code is like this

process(cnt,tmp,rst)
begin
if rst='1' then
cnt <= "0000";
tmp <= "000";
i <= 0;
else
w : while i< 8 loop
tmp <= tmp+1;
cnt <= cnt+1;
i <= i + 1;
end loop w;
end if;
end process;
Click to expand...
Yeeesh! Where are people learning how to write such crappy code? Let
me guess: you're a software guy?

Anyways, you don't want a while loop, or a for loop, or in fact any
loop at all. You need to THINK HARDWARE. What sort of hardware do you
think your synthesize will do with your code? First of all, you
probably want to use a clock to synchronize everything; as it is now,
you have a big combinatorial mess.

Maybe something like:

mycnt : process (clk, rst) is
begin
if (rst = '1') then
cnt <= "0000";
tmp <= "000";
i <= 0;
elsif rising_edge(clk) then
if i < 8 then
cnt <= cnt + 1;
tmp <= tmp + 1;
i <= i + 1;
end if;
end if;
end process mycnt;

It's left as an exercise for the reader to choose the proper type for
cnt, tmp and i, as well as to figure out how to clear the counter once
i is 8.

-a
 
hi,
my problem is not with the code that how to make it executable.
i've got result without 'while' loop.
actually, i have to make a design with while loop only & to check it
with synplify tool that it will synthesize it or not.
i've check all conditions within while loop, such as i took
variables, signals, std_logic_vector, integer, exit, with & without
clock & rst condition etc., but the tool is giving following error
continuously

"while loop is not terminating?you can set the maximum number of loop
iterations with the syn_loop limit attribute -- attach it to the loop
label:file path.."

this compiler error is coming with every condition.
what to do?
thanx.
 
jiten wrote:
hi,
my problem is not with the code that how to make it executable.
i've got result without 'while' loop.
Click to expand...
As Mike says, you've already got your answer.

actually, i have to make a design with while loop only & to check it
with synplify tool that it will synthesize it or not.
Click to expand...
Why do you have to do this? Homework assignment?

i've check all conditions within while loop, such as i took
variables, signals, std_logic_vector, integer, exit, with & without
clock & rst condition etc., but the tool is giving following error
continuously

"while loop is not terminating?you can set the maximum number of loop
iterations with the syn_loop limit attribute -- attach it to the loop
label:file path.."

this compiler error is coming with every condition.
what to do?
Click to expand...
you've already been told what to do. Accept reality and move forward.

-a
 
hi,
i am ready to accept the truth.
but please tell me the truth.
i just want to know
IS WHILE LOOP IS SYNTHESIZABLE WITH SYNPLIFY-PRO TOOL OR NOT?

if anybody has worked with this synplify-pro tool.
plz share his/her experience & tell me while loop is synthesizable
or not?

thanx all.
 
hi all,
I've got solution.
Just use an wait on statement in the while loop.
thanx n regards.
 
jiten wrote:
hi all,
I've got solution.
Just use an wait on statement in the while loop.
thanx n regards.
Click to expand...
I'm interested in seeing what sort of ugly hardware results from your
stubborn insistence on using while loops in synthesizable code.

In Other Words: just because it CAN be done, doesn't mean it SHOULD be
done.

-a
 
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