While compiling

[Be myself]

Once I take one VHDL code into ModelSim,
make the tool compiling code,I found some syntax error message.
Thus this action failed.

While,the same code can pass the verification of max-plus2 .
.....
I can't figure out this result. ???
--
 Ą°ľoŤHŻ¸: ş~ŻŤ¤pŻ¸ <bbs.ee.nsysu.edu.tw>
 Ąť From: pailiou.ee.nsysu.edu.tw

 

[Brent Hayhoe]

Be myself wrote:

Once I take one VHDL code into ModelSim,
make the tool compiling code,I found some syntax error message.
Thus this action failed.

While,the same code can pass the verification of max-plus2 .
....
I can't figure out this result. ???

Neither can anyone else without some more information than this!

--
 Ą°ľoŤHŻ¸: ş~ŻŤ¤pŻ¸ <bbs.ee.nsysu.edu.tw>
 Ąť From: pailiou.ee.nsysu.edu.tw

--

Regards,

Brent Hayhoe.

Aftonroy Limited
Email: <A
HREF="mailto:Brent.Hayhoe@Aftonroy.com">

 

[Tero Kapanen]

"Brent Hayhoe" <For_My_Address@see.my.sig> wrote in message
news:boq2ll$nbp$1@news7.svr.pol.co.uk...

I can't figure out this result. ???

Neither can anyone else without some more information than this!

I want to try anyway.

Check that you have VHDL-93 enabled.

Right-click the vhdl-file, Properties and under VHDL tab there is "use 1993
Language Syntax".

- tero